Merge "drm/msm/sde: increase max CTLs to 6" (1fe3424e) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/Kconfig

+0 −1

Original line number	Diff line number	Diff line
		@@ -14,7 +14,6 @@ config DRM_MSM
		select QCOM_SCM
		select SND_SOC_HDMI_CODEC if SND_SOC
		select SYNC_FILE
		select HDCP_QSEECOM
		select MSM_EXT_DISPLAY
		default y
		help

drivers/gpu/drm/msm/dp/dp_display.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -237,8 +237,9 @@ static void dp_display_update_hdcp_info(struct dp_display_private *dp)
		pr_debug("hdcp2p2: %s\n",
		dp->hdcp.hdcp2_present ? "supported" : "not supported");

		if (!dp->hdcp.hdcp2_present) {
		dp->hdcp.hdcp1_present = hdcp1_check_if_supported_load_app();
		if (IS_ENABLED(CONFIG_HDCP_QSEECOM) && !dp->hdcp.hdcp2_present) {
		dp->hdcp.hdcp1_present =
		hdcp1_check_if_supported_load_app();

		if (dp->hdcp.hdcp1_present) {
		fd = dp->hdcp.hdcp1;

drivers/gpu/drm/msm/dp/dp_hdcp2p2.c

+9 −4

Original line number	Diff line number	Diff line
		/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -861,11 +861,16 @@ void sde_dp_hdcp2p2_init(struct sde_hdcp_init_data init_data)
		register_data.device_type = HDCP_TXMTR_DP;
		register_data.client_ctx = ctrl;


		if (IS_ENABLED(CONFIG_HDCP_QSEECOM)) {
		rc = hdcp_library_register(&register_data);
		if (rc) {
		pr_err("Unable to register with HDCP 2.2 library\n");
		goto error;
		}
		} else {
		goto error;
		}

		kthread_init_worker(&ctrl->worker);

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+8 −6

Original line number	Diff line number	Diff line
		/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -116,6 +116,7 @@
		#define SDE_INTR_CTL_2_START BIT(11)
		#define SDE_INTR_CTL_3_START BIT(12)
		#define SDE_INTR_CTL_4_START BIT(13)
		#define SDE_INTR_CTL_5_START BIT(23)

		/**
		* Concurrent WB overflow interrupt status bit definitions
		@@ -337,7 +338,7 @@ static const struct sde_irq_type sde_irq_map[] = {
		/* irq_idx: 40 */
		{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
		SDE_INTR_PING_PONG_S0_RD_PTR, 1},
		/* irq_idx: 41-45 */
		/* irq_idx: 41-46 */
		{ SDE_IRQ_TYPE_CTL_START, CTL_0,
		SDE_INTR_CTL_0_START, 1},
		{ SDE_IRQ_TYPE_CTL_START, CTL_1,
		@@ -348,10 +349,12 @@ static const struct sde_irq_type sde_irq_map[] = {
		SDE_INTR_CTL_3_START, 1},
		{ SDE_IRQ_TYPE_CTL_START, CTL_4,
		SDE_INTR_CTL_4_START, 1},
		/* irq_idx: 46-47 */
		{ SDE_IRQ_TYPE_CTL_START, CTL_5,
		SDE_INTR_CTL_5_START, 1},
		/* irq_idx: 47-48 */
		{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_2, SDE_INTR_CWB_2_OVERFLOW, 1},
		{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_3, SDE_INTR_CWB_3_OVERFLOW, 1},
		/* irq_idx: 48-51 */
		/* irq_idx: 49-52 */
		{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
		SDE_INTR_PING_PONG_0_TEAR_DETECTED, 1},
		{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
		@@ -360,12 +363,11 @@ static const struct sde_irq_type sde_irq_map[] = {
		SDE_INTR_PING_PONG_2_TEAR_DETECTED, 1},
		{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
		SDE_INTR_PING_PONG_3_TEAR_DETECTED, 1},
		/* irq_idx: 52-55 */
		/* irq_idx: 53-55 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
		{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
		SDE_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
		/* irq_idx: 56-59 */
		{ SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
		SDE_INTR_PING_PONG_0_TE_DETECTED, 1},

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -191,6 +191,7 @@ enum sde_ctl {
		CTL_2,
		CTL_3,
		CTL_4,
		CTL_5,
		CTL_MAX
		};