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Commit 92757510 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: kgsl: Cleanup the device tree probing for memory pools"

parents 721c41dd 880a71f5

drivers/gpu/msm/adreno.c

+18 −46
Original line number Diff line number Diff line
@@ -223,15 +223,14 @@ unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb) 
static void __iomem *efuse_base;

static size_t efuse_len;



int adreno_efuse_map(struct adreno_device *adreno_dev)

int adreno_efuse_map(struct platform_device *pdev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct resource *res;



	if (efuse_base != NULL)

		return 0;



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

		"qfprom_memory");



	if (res == NULL)
@@ -245,7 +244,7 @@ int adreno_efuse_map(struct adreno_device *adreno_dev) 
	return 0;

}



void adreno_efuse_unmap(struct adreno_device *adreno_dev)

void adreno_efuse_unmap(void)

{

	if (efuse_base != NULL) {

		iounmap(efuse_base);
@@ -254,8 +253,7 @@ void adreno_efuse_unmap(struct adreno_device *adreno_dev) 
	}

}



int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset,

		unsigned int *val)

int adreno_efuse_read_u32(unsigned int offset, unsigned int *val)

{

	if (efuse_base == NULL)

		return -ENODEV;
@@ -263,11 +261,9 @@ int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset, 
	if (offset >= efuse_len)

		return -ERANGE;



	if (val != NULL) {

	*val = readl_relaxed(efuse_base + offset);

	/* Make sure memory is updated before returning */

	rmb();

	}



	return 0;

}
@@ -1256,27 +1252,28 @@ static void adreno_isense_probe(struct kgsl_device *device) 


static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned int val;

	unsigned int soc_hw_rev[3];

	int ret;



	if (of_property_read_u32_array(

		KGSL_DEVICE(adreno_dev)->pdev->dev.of_node,

		device->pdev->dev.of_node,

		"qcom,soc-hw-rev-efuse", soc_hw_rev, 3))

		return;



	ret = adreno_efuse_map(adreno_dev);

	ret = adreno_efuse_map(device->pdev);

	if (ret) {

		dev_err(KGSL_DEVICE(adreno_dev)->dev,

		dev_err(device->dev,

			"Unable to map hardware revision fuse: ret=%d\n", ret);

		return;

	}



	ret = adreno_efuse_read_u32(adreno_dev, soc_hw_rev[0], &val);

	adreno_efuse_unmap(adreno_dev);

	ret = adreno_efuse_read_u32(soc_hw_rev[0], &val);

	adreno_efuse_unmap();



	if (ret) {

		dev_err(KGSL_DEVICE(adreno_dev)->dev,

		dev_err(device->dev,

			"Unable to read hardware revision fuse: ret=%d\n", ret);

		return;

	}
@@ -1298,11 +1295,11 @@ static bool adreno_is_gpu_disabled(struct adreno_device *adreno_dev) 
	 * Read the fuse value to disable GPU driver if fuse

	 * is blown. By default(fuse value is 0) GPU is enabled.

	 */

	if (adreno_efuse_map(adreno_dev))

	if (adreno_efuse_map(device->pdev))

		return false;



	ret = adreno_efuse_read_u32(adreno_dev, pte_row0_msb[0], &row0);

	adreno_efuse_unmap(adreno_dev);

	ret = adreno_efuse_read_u32(pte_row0_msb[0], &row0);

	adreno_efuse_unmap();



	if (ret)

		return false;
@@ -1822,7 +1819,7 @@ static void _set_secvid(struct kgsl_device *device) 
	}

}



static int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

				struct adreno_ringbuffer *rb)

{

	unsigned int *cmds;
@@ -1844,31 +1841,6 @@ static int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev, 
	return ret;

}



int adreno_set_unsecured_mode(struct adreno_device *adreno_dev,

		struct adreno_ringbuffer *rb)

{

	int ret = 0;



	if (!adreno_is_a5xx(adreno_dev) && !adreno_is_a6xx(adreno_dev))

		return -EINVAL;



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS) &&

			adreno_is_a5xx(adreno_dev)) {

		ret = a5xx_critical_packet_submit(adreno_dev, rb);

		if (ret)

			return ret;

	}



	/* GPU comes up in secured mode, make it unsecured by default */

	if (adreno_dev->zap_loaded)

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);

	else

		adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TRUST_CONTROL, 0x0);



	return ret;

}



static void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)

{

	int i;

drivers/gpu/msm/adreno.h

+14 −10
Original line number Diff line number Diff line
@@ -663,8 +663,6 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

	ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,

	ADRENO_REG_RBBM_SECVID_TRUST_CONFIG,

	ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,
@@ -913,10 +911,17 @@ long adreno_ioctl_helper(struct kgsl_device_private *dev_priv, 
		unsigned int cmd, unsigned long arg,

		const struct kgsl_ioctl *cmds, int len);



int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,

		struct adreno_ringbuffer *rb);

int adreno_set_unsecured_mode(struct adreno_device *adreno_dev,

/*

 * adreno_switch_to_unsecure_mode - Execute a zap shader

 * @adreno_dev: An Adreno GPU handle

 * @rb: The ringbuffer to execute on

 *

 * Execute the zap shader from the CP to take the GPU out of secure mode.

 * Return: 0 on success or negative on failure

 */

int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

				struct adreno_ringbuffer *rb);



void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str);

int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);

int adreno_idle(struct kgsl_device *device);
@@ -955,10 +960,9 @@ long adreno_ioctl_perfcounter_get(struct kgsl_device_private *dev_priv, 
long adreno_ioctl_perfcounter_put(struct kgsl_device_private *dev_priv,

	unsigned int cmd, void *data);



int adreno_efuse_map(struct adreno_device *adreno_dev);

int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset,

		unsigned int *val);

void adreno_efuse_unmap(struct adreno_device *adreno_dev);

int adreno_efuse_map(struct platform_device *pdev);

int adreno_efuse_read_u32(unsigned int offset, unsigned int *val);

void adreno_efuse_unmap(void);



bool adreno_is_cx_dbgc_register(struct kgsl_device *device,

		unsigned int offset);

drivers/gpu/msm/adreno_a3xx.c

+3 −3
Original line number Diff line number Diff line
@@ -135,7 +135,7 @@ static void a3xx_efuse_speed_bin(struct adreno_device *adreno_dev) 
		"qcom,gpu-speed-bin", speed_bin, 3))

		return;



	adreno_efuse_read_u32(adreno_dev, speed_bin[0], &val);

	adreno_efuse_read_u32(speed_bin[0], &val);



	adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2];

}
@@ -151,7 +151,7 @@ static void a3xx_check_features(struct adreno_device *adreno_dev) 
{

	unsigned int i;



	if (adreno_efuse_map(adreno_dev))

	if (adreno_efuse_map(KGSL_DEVICE(adreno_dev)->pdev))

		return;



	for (i = 0; i < ARRAY_SIZE(a3xx_efuse_funcs); i++) {
@@ -159,7 +159,7 @@ static void a3xx_check_features(struct adreno_device *adreno_dev) 
			a3xx_efuse_funcs[i].func(adreno_dev);

	}



	adreno_efuse_unmap(adreno_dev);

	adreno_efuse_unmap();

}



/**

drivers/gpu/msm/adreno_a5xx.c

+22 −14
Original line number Diff line number Diff line
@@ -49,11 +49,9 @@ static void a530_efuse_leakage(struct adreno_device *adreno_dev) 
	unsigned int row0, row2;

	unsigned int multiplier, gfx_active, leakage_pwr_on, coeff;



	adreno_efuse_read_u32(adreno_dev,

		A530_QFPROM_RAW_PTE_ROW0_MSB, &row0);

	adreno_efuse_read_u32(A530_QFPROM_RAW_PTE_ROW0_MSB, &row0);



	adreno_efuse_read_u32(adreno_dev,

		A530_QFPROM_RAW_PTE_ROW2_MSB, &row2);

	adreno_efuse_read_u32(A530_QFPROM_RAW_PTE_ROW2_MSB, &row2);



	multiplier = (row0 >> 1) & 0x3;

	gfx_active = (row2 >> 2) & 0xFF;
@@ -78,7 +76,7 @@ static void a530_efuse_speed_bin(struct adreno_device *adreno_dev) 
		"qcom,gpu-speed-bin", speed_bin, 3))

		return;



	adreno_efuse_read_u32(adreno_dev, speed_bin[0], &val);

	adreno_efuse_read_u32(speed_bin[0], &val);



	adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2];

}
@@ -98,7 +96,7 @@ static void a5xx_check_features(struct adreno_device *adreno_dev) 
{

	unsigned int i;



	if (adreno_efuse_map(adreno_dev))

	if (adreno_efuse_map(KGSL_DEVICE(adreno_dev)->pdev))

		return;



	for (i = 0; i < ARRAY_SIZE(a5xx_efuse_funcs); i++) {
@@ -106,7 +104,7 @@ static void a5xx_check_features(struct adreno_device *adreno_dev) 
			a5xx_efuse_funcs[i].func(adreno_dev);

	}



	adreno_efuse_unmap(adreno_dev);

	adreno_efuse_unmap();

}



static void a5xx_platform_setup(struct adreno_device *adreno_dev)
@@ -1811,7 +1809,7 @@ static void _set_ordinals(struct adreno_device *adreno_dev, 
		*cmds++ = 0x0;

}



int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,

static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,

					struct adreno_ringbuffer *rb)

{

	unsigned int *cmds;
@@ -1907,8 +1905,22 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev) 
	if (ret)

		return ret;



	/* GPU comes up in secured mode, make it unsecured by default */

	ret = adreno_set_unsecured_mode(adreno_dev, rb);

	/* Run the critical packets if we need to */

	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS)) {

		ret = a5xx_critical_packet_submit(adreno_dev, rb);

		if (ret)

			return ret;

	}



	/*

	 * Try to execute the zap shader if it exists, otherwise just try

	 * directly writing to the control register

	 */

	if (!adreno_dev->zap_loaded)

		kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0);

	else

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);



	if (ret)

		return ret;
@@ -2433,10 +2445,6 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A5XX_RBBM_PERFCTR_LOAD_VALUE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

				A5XX_RBBM_PERFCTR_LOAD_VALUE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,

				A5XX_RBBM_SECVID_TRUST_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONFIG,

				A5XX_RBBM_SECVID_TRUST_CONFIG),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

				A5XX_RBBM_SECVID_TSB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

drivers/gpu/msm/adreno_a6xx.c

+12 −7
Original line number Diff line number Diff line
@@ -816,8 +816,15 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev) 
	if (ret)

		return ret;



	/* GPU comes up in secured mode, make it unsecured by default */

	ret = adreno_set_unsecured_mode(adreno_dev, rb);

	/*

	 * Take the GPU out of secure mode. Try the zap shader if it is loaded,

	 * otherwise just try to write directly to the secure control register

	 */

	if (!adreno_dev->zap_loaded)

		kgsl_regwrite(device, A6XX_RBBM_SECVID_TRUST_CNTL, 0);

	else

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);



	if (ret)

		return ret;
@@ -2168,7 +2175,7 @@ static void a6xx_efuse_speed_bin(struct adreno_device *adreno_dev) 
		"qcom,gpu-speed-bin", speed_bin, 3))

		return;



	adreno_efuse_read_u32(adreno_dev, speed_bin[0], &val);

	adreno_efuse_read_u32(speed_bin[0], &val);



	adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2];

}
@@ -2185,14 +2192,14 @@ static void a6xx_check_features(struct adreno_device *adreno_dev) 
{

	unsigned int i;



	if (adreno_efuse_map(adreno_dev))

	if (adreno_efuse_map(KGSL_DEVICE(adreno_dev)->pdev))

		return;

	for (i = 0; i < ARRAY_SIZE(a6xx_efuse_funcs); i++) {

		if (a6xx_efuse_funcs[i].check(adreno_dev))

			a6xx_efuse_funcs[i].func(adreno_dev);

	}



	adreno_efuse_unmap(adreno_dev);

	adreno_efuse_unmap();

}

static void a6xx_platform_setup(struct adreno_device *adreno_dev)

{
@@ -2370,8 +2377,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A6XX_GMU_CM3_CFG),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,

				A6XX_GMU_RBBM_INT_UNMASKED_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,

				A6XX_RBBM_SECVID_TRUST_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

				A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,