Merge "msm: kgsl: Make the a6xx mbox client static" (721c41dd) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -3,6 +3,7 @@ config QCOM_KGSL
		tristate "Qualcomm Technologies, Inc. 3D Graphics driver"
		depends on ARCH_QCOM
		depends on QCOM_QFPROM
		select MSM_SUBSYSTEM_RESTART
		help
		3D graphics driver for the Adreno family of GPUs from QTI.
		Required to use hardware accelerated OpenGL, compute and Vulkan

drivers/gpu/msm/adreno.c

+18 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@
		#include <linux/regulator/consumer.h>
		#include <linux/nvmem-consumer.h>
		#include <linux/soc/qcom/llcc-qcom.h>
		#include <soc/qcom/subsystem_restart.h>

		#include "adreno.h"
		#include "adreno_a3xx.h"
		@@ -124,6 +125,23 @@ int adreno_get_firmware(struct adreno_device *adreno_dev,
		return ret;
		}


		int adreno_zap_shader_load(struct adreno_device *adreno_dev,
		const char *name)
		{
		void *ptr;

		if (!name \|\| adreno_dev->zap_loaded)
		return 0;

		ptr = subsystem_get(name);

		if (!IS_ERR(ptr))
		adreno_dev->zap_loaded = true;

		return PTR_ERR_OR_ZERO(ptr);
		}

		void adreno_reglist_write(struct adreno_device *adreno_dev,
		const struct adreno_reglist *list, u32 count)
		{

drivers/gpu/msm/adreno.h

+26 −1

Original line number	Diff line number	Diff line
		@@ -769,7 +769,6 @@ struct adreno_gpudev {
		struct adreno_coresight *coresight[2];

		struct adreno_irq *irq;
		int num_prio_levels;
		unsigned int vbif_xin_halt_ctrl0_mask;
		unsigned int gbif_client_halt_mask;
		unsigned int gbif_arb_halt_mask;
		@@ -1683,6 +1682,21 @@ static inline void adreno_deassert_gbif_halt(struct adreno_device *adreno_dev)
		ADRENO_REG_RBBM_GBIF_HALT, 0x0);
		}
		}

		/**
		* adreno_move_preempt_state - Update the preemption state
		* @adreno_dev: An Adreno GPU device handle
		* @old: The current state of the preemption
		* @new: The new state of the preemption
		*
		* Return: True if the state was updated or false if not
		*/
		static inline bool adreno_move_preempt_state(struct adreno_device *adreno_dev,
		enum adreno_preempt_states old, enum adreno_preempt_states new)
		{
		return (atomic_cmpxchg(&adreno_dev->preempt.state, old, new) == old);
		}

		void adreno_gmu_clear_and_unmask_irqs(struct adreno_device *adreno_dev);
		void adreno_gmu_mask_and_clear_irqs(struct adreno_device *adreno_dev);
		int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		@@ -1705,4 +1719,15 @@ void adreno_gmu_send_nmi(struct adreno_device *adreno_dev);
		*/
		int adreno_get_firmware(struct adreno_device *adreno_dev,
		const char fwfile, struct adreno_firmware firmware);
		/**
		* adreno_zap_shader_load - Helper function for loading the zap shader
		* adreno_dev: A handle to an Adreno GPU device
		* name: Name of the zap shader to load
		*
		* A target indepedent helper function for loading the zap shader.
		*
		* Return: 0 on success or negative on failure.
		*/
		int adreno_zap_shader_load(struct adreno_device *adreno_dev,
		const char *name);
		#endif /__ADRENO_H /

drivers/gpu/msm/adreno_a3xx.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -1402,7 +1402,6 @@ struct adreno_gpudev adreno_a3xx_gpudev = {
		.perfcounters = &a3xx_perfcounters,
		.irq = &a3xx_irq,
		.irq_trace = trace_kgsl_a3xx_irq_status,
		.num_prio_levels = 1,
		.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,
		.platform_setup = a3xx_platform_setup,
		.rb_start = a3xx_rb_start,

drivers/gpu/msm/adreno_a5xx.c

+14 −28

Original line number	Diff line number	Diff line
		@@ -9,7 +9,6 @@
		#include <linux/of.h>
		#include <linux/qcom_scm.h>
		#include <linux/slab.h>
		#include <soc/qcom/subsystem_restart.h>

		#include "adreno.h"
		#include "adreno_a5xx.h"
		@@ -1681,13 +1680,23 @@ static int a5xx_gpmu_init(struct adreno_device *adreno_dev)
		return 0;
		}

		static int a5xx_zap_shader_resume(struct kgsl_device *device)
		{
		int ret = qcom_scm_set_remote_state(0, 13);

		if (ret)
		dev_err(device->dev,
		"SCM zap resume call failed: %d\n", ret);

		return ret;
		}

		/*
		* a5xx_microcode_load() - Load microcode
		* @adreno_dev: Pointer to adreno device
		*/
		static int a5xx_microcode_load(struct adreno_device *adreno_dev)
		{
		void *ptr;
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);
		struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);
		@@ -1713,32 +1722,11 @@ static int a5xx_microcode_load(struct adreno_device *adreno_dev)
		if (!device->mmu.secured)
		return 0;

		/*
		* Resume call to write the zap shader base address into the
		* appropriate register,
		* skip if retention is supported for the CPZ register
		*/
		if (adreno_dev->zap_loaded && !(ADRENO_FEATURE(adreno_dev,
		ADRENO_CPZ_RETENTION))) {
		int ret = qcom_scm_set_remote_state(0, 13);

		if (ret)
		dev_err(KGSL_DEVICE(adreno_dev)->dev,
		"Unable to resume the zap shader: %d\n", ret);
		return ret;
		}

		/* Load the zap shader firmware through PIL if its available */
		if (a5xx_core->zap_name && !adreno_dev->zap_loaded) {
		ptr = subsystem_get(a5xx_core->zap_name);
		ADRENO_CPZ_RETENTION)))
		return a5xx_zap_shader_resume(device);

		/* Return error if the zap shader cannot be loaded */
		if (IS_ERR_OR_NULL(ptr))
		return (ptr == NULL) ? -ENODEV : PTR_ERR(ptr);
		adreno_dev->zap_loaded = 1;
		}

		return 0;
		return adreno_zap_shader_load(adreno_dev, a5xx_core->zap_name);
		}

		static int _me_init_ucode_workarounds(struct adreno_device *adreno_dev)
		@@ -3025,7 +3013,6 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
		.snapshot = a5xx_snapshot,
		.irq = &a5xx_irq,
		.irq_trace = trace_kgsl_a5xx_irq_status,
		.num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS,
		.platform_setup = a5xx_platform_setup,
		.init = a5xx_init,
		.remove = a5xx_remove,
		@@ -3045,7 +3032,6 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
		.preemption_post_ibsubmit =
		a5xx_preemption_post_ibsubmit,
		.preemption_init = a5xx_preemption_init,
		.preemption_close = a5xx_preemption_close,
		.preemption_schedule = a5xx_preemption_schedule,
		.clk_set_options = a5xx_clk_set_options,
		.read_alwayson = a5xx_read_alwayson,