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Commit 6ba06de0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add DPC and capacity-dmips-mhz for Holi"

parents 5a3f66a8 53fae8ab

qcom/holi.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ 
			reg = <0x0 0x0>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -44,6 +46,8 @@ 
			reg = <0x0 0x100>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -58,6 +62,8 @@ 
			reg = <0x0 0x200>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";
@@ -72,6 +78,8 @@ 
			reg = <0x0 0x300>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_3>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";
@@ -86,6 +94,8 @@ 
			reg = <0x0 0x400>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";
@@ -100,6 +110,8 @@ 
			reg = <0x0 0x500>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";
@@ -114,6 +126,8 @@ 
			reg = <0x0 0x600>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <324>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";
@@ -128,6 +142,8 @@ 
			reg = <0x0 0x700>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <324>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";