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Commit 5a3f66a8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm:Add fastrpc and cdsp/adsp device node"

parents 6d6d845d db1e505e

qcom/shima.dtsi

+181 −0
Original line number Diff line number Diff line
@@ -267,6 +267,14 @@ 
			reg = <0x0 0x88f00000 0x0 0x1e00000>;

		};



		adsp_mem: adsp_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;

			reusable;

			alignment = <0x0 0x400000>;

			size = <0x0 0xC00000>;

		};



		pil_wlan_mem: wlan@8ad00000 {

			no-map;

			reg = <0x0 0x8ad00000 0x0 0xa00000>;
@@ -1273,6 +1281,179 @@ 
		mboxes = <&qmp_aop 0>;

		mbox-names = "cdsp-pil";

	};



	qcom,msm-adsprpc-mem {

		compatible = "qcom,msm-adsprpc-mem-region";

		memory-region = <&adsp_mem>;

		restrict-access;

	};



	msm_fastrpc: qcom,msm_fastrpc {

		compatible = "qcom,msm-fastrpc-compute";

		qcom,adsp-remoteheap-vmid = <22 37>;

		qcom,fastrpc-adsp-audio-pdr;

		qcom,fastrpc-adsp-sensors-pdr;

		qcom,rpc-latency-us = <235>;



		qcom,msm_fastrpc_compute_cb1 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2961 0x0400>,

					 <&apps_smmu 0x1981 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb2 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2962 0x0400>,

					 <&apps_smmu 0x1982 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb3 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2963 0x0400>,

					 <&apps_smmu 0x1983 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb4 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2964 0x0400>,

					 <&apps_smmu 0x1984 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb5 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2965 0x0400>,

					 <&apps_smmu 0x1985 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb6 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x02966 0x0400>,

					 <&apps_smmu 0x1986 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb7 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2967 0x0400>,

					 <&apps_smmu 0x1987 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb8 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x2968 0x0400>,

					 <&apps_smmu 0x1988 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb9 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			qcom,secure-context-bank;

			iommus = <&apps_smmu 0x2969 0x0400>,

					 <&apps_smmu 0x1989 0x0420>;

			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb10 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x2003 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb11 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x2004 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb12 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x2005 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb13 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x198B 0x0420>,

					 <&apps_smmu 0x296B 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb14 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x198C 0x0420>,

					 <&apps_smmu 0x296C 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb15 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x198D 0x0420>,

					 <&apps_smmu 0x296D 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb16 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x198E 0x0420>,

					 <&apps_smmu 0x296E 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};

	};

};



#include "shima-pinctrl.dtsi"