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Commit 53fae8ab authored by Lingutla Chandrasekhar's avatar Lingutla Chandrasekhar
Browse files

ARM: dts: msm: Add DPC and capacity-dmips-mhz for Holi 

Add Dynamic power co-efficient (DPC) and capacity-dmips-mhz values,
which are used by energy aware scheduler for taskplacement decisions.

Change-Id: I2eff5f16dde27eb4728cba5aa6b58145ca6edb11
parent 82361dc0

qcom/holi.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
			reg = <0x0 0x0>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -43,6 +45,8 @@ 
			reg = <0x0 0x100>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -57,6 +61,8 @@ 
			reg = <0x0 0x200>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";
@@ -71,6 +77,8 @@ 
			reg = <0x0 0x300>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_3>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";
@@ -85,6 +93,8 @@ 
			reg = <0x0 0x400>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";
@@ -99,6 +109,8 @@ 
			reg = <0x0 0x500>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";
@@ -113,6 +125,8 @@ 
			reg = <0x0 0x600>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <324>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";
@@ -127,6 +141,8 @@ 
			reg = <0x0 0x700>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x50000000>;

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <324>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";