Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 69a06e49 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-artpec',... 

Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-artpec', 'pci/host-designware', 'pci/host-hv', 'pci/host-keystone', 'pci/host-rcar', 'pci/host-rockchip', 'pci/host-tegra' and 'pci/host-xilinx' into next

* pci/host-aardvark:
  PCI: aardvark: Remove redundant dev_err call in advk_pcie_probe()

* pci/host-altera:
  PCI: altera: Remove redundant platform_get_resource() return value check
  PCI: altera: Move retrain from fixup to altera_pcie_host_init()
  PCI: altera: Rework config accessors for use without a struct pci_bus
  PCI: altera: Poll for link training status after retraining the link

* pci/host-artpec:
  PCI: artpec6: Drop __init from artpec6_add_pcie_port()

* pci/host-designware:
  PCI: designware: Remove redundant platform_get_resource() return value check
  PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs'
  PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2
  PCI: designware: Check LTSSM training bit before deciding link is up
  PCI: designware: Add iATU Unroll feature
  PCI: designware: Wait for iATU enable
  PCI: designware: Move link wait definitions to .c file
  PCI: designware: Return data directly from dw_pcie_readl_rc()

* pci/host-hv:
  PCI: hv: Handle hv_pci_generic_compl() error case
  PCI: hv: Handle vmbus_sendpacket() failure in hv_compose_msi_msg()
  PCI: hv: Remove the unused 'wrk' in struct hv_pcibus_device
  PCI: hv: Use pci_function_description[0] in struct definitions
  PCI: hv: Use zero-length array in struct pci_packet
  PCI: hv: Use list_move_tail() instead of list_del() + list_add_tail()

* pci/host-keystone:
  PCI: keystone: Propagate request_irq() failure

* pci/host-rcar:
  PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot
  PCI: rcar: Fix some checkpatch warnings
  PCI: rcar: Add multi-MSI support
  PCI: rcar: Don't disable/unprepare clocks on prepare/enable failure
  PCI: rcar: Consolidate register space lookup and ioremap

* pci/host-rockchip:
  PCI: rockchip: Fix wrong transmitted FTS count
  PCI: rockchip: Improve the deassert sequence of four reset pins
  PCI: rockchip: Increase the Max Credit update interval
  PCI: rockchip: Add Rockchip PCIe controller support
  dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller

* pci/host-tegra:
  PCI: tegra: Use of_device_get_match_data()
  PCI: tegra: Remove redundant _data suffix

* pci/host-xilinx:
  microblaze/PCI: Add multidomain support for procfs
  PCI: xilinx: Dispose of MSI virtual IRQ
  PCI: xilinx: Clear correct MSI set bit
  PCI: xilinx: Clear interrupt register for invalid interrupt
  PCI: xilinx: Keep both legacy and MSI interrupt domain references
  PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask
  PCI: xilinx-nwl: Expand error logging

Conflicts:
	drivers/pci/host/pcie-xilinx.c
parents 930ffc03 8b22335a 6c8b1208 b58ddf17 639c5323 a5b45b7b 8116acce b3327f7f ca198908 c460af94 9413d968

Documentation/devicetree/bindings/pci/designware-pcie.txt

+3 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ Required properties: 
- num-lanes: number of lanes to use



Optional properties:

- num-viewport: number of view ports configured in hardware.  If a platform

  does not specify it, the driver assumes 2.

- num-lanes: number of lanes to use (this property should be specified unless

  the link is brought already up in BIOS)

- reset-gpio: gpio pin number of power good signal
@@ -44,4 +46,5 @@ Example configuration: 
		interrupts = <25>, <24>;

		#interrupt-cells = <1>;

		num-lanes = <1>;

		num-viewport = <3>;

	};

Documentation/devicetree/bindings/pci/rockchip-pcie.txt

0 → 100644
+106 −0
Original line number Diff line number Diff line 
* Rockchip AXI PCIe Root Port Bridge DT description



Required properties:

- #address-cells: Address representation for root ports, set to <3>

- #size-cells: Size representation for root ports, set to <2>

- #interrupt-cells: specifies the number of cells needed to encode an

		interrupt source. The value must be 1.

- compatible: Should contain "rockchip,rk3399-pcie"

- reg: Two register ranges as listed in the reg-names property

- reg-names: Must include the following names

	- "axi-base"

	- "apb-base"

- clocks: Must contain an entry for each entry in clock-names.

		See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

	- "aclk"

	- "aclk-perf"

	- "hclk"

	- "pm"

- msi-map: Maps a Requester ID to an MSI controller and associated

	msi-specifier data. See ./pci-msi.txt

- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.

- phy-names:  MUST be "pcie-phy".

- interrupts: Three interrupt entries must be specified.

- interrupt-names: Must include the following names

	- "sys"

	- "legacy"

	- "client"

- resets: Must contain five entries for each entry in reset-names.

	   See ../reset/reset.txt for details.

- reset-names: Must include the following names

	- "core"

	- "mgmt"

	- "mgmt-sticky"

	- "pipe"

- pinctrl-names : The pin control state names

- pinctrl-0: The "default" pinctrl state

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.

- interrupt-map-mask and interrupt-map: standard PCI properties



Optional Property:

- ep-gpios: contain the entry for pre-reset gpio

- num-lanes: number of lanes to use

- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.

- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.

- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.



*Interrupt controller child node*

The core controller provides a single interrupt for legacy INTx. The PCIe node

should contain an interrupt controller node as a target for the PCI

'interrupt-map' property. This node represents the domain at which the four

INTx interrupts are decoded and routed.





Required properties for Interrupt controller child node:

- interrupt-controller: identifies the node as an interrupt controller

- #address-cells: specifies the number of cells needed to encode an

	address. The value must be 0.

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.



Example:



pcie0: pcie@f8000000 {

	compatible = "rockchip,rk3399-pcie";

	#address-cells = <3>;

	#size-cells = <2>;

	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,

		 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;

	clock-names = "aclk", "aclk-perf",

		      "hclk", "pm";

	bus-range = <0x0 0x1>;

	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,

		     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,

		     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;

	interrupt-names = "sys", "legacy", "client";

	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;

	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;

	assigned-clock-rates = <100000000>;

	ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;

	ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000

		  0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;

	num-lanes = <4>;

	msi-map = <0x0 &its 0x0 0x1000>;

	reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;

	reg-names = "axi-base", "apb-base";

	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,

		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;

	reset-names = "core", "mgmt", "mgmt-sticky", "pipe";

	phys = <&pcie_phy>;

	phy-names = "pcie-phy";

	pinctrl-names = "default";

	pinctrl-0 = <&pcie_clkreq>;

	#interrupt-cells = <1>;

	interrupt-map-mask = <0 0 0 7>;

	interrupt-map = <0 0 0 1 &pcie0_intc 0>,

			<0 0 0 2 &pcie0_intc 1>,

			<0 0 0 3 &pcie0_intc 2>,

			<0 0 0 4 &pcie0_intc 3>;

	pcie0_intc: interrupt-controller {

		interrupt-controller;

		#address-cells = <0>;

		#interrupt-cells = <1>;

	};

};

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -9083,6 +9083,15 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/hisilicon-pcie.txt

F:	drivers/pci/host/pcie-hisi.c



PCIE DRIVER FOR ROCKCHIP

M:	Shawn Lin <shawn.lin@rock-chips.com>

M:	Wenrui Li <wenrui.li@rock-chips.com>

L:	linux-pci@vger.kernel.org

L:	linux-rockchip@lists.infradead.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/rockchip-pcie.txt

F:	drivers/pci/host/pcie-rockchip.c



PCIE DRIVER FOR QUALCOMM MSM

M:     Stanimir Varbanov <svarbanov@mm-sol.com>

L:     linux-pci@vger.kernel.org

arch/microblaze/pci/pci-common.c

+2 −2
Original line number Diff line number Diff line
@@ -632,10 +632,10 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose, 
	}

}



/* Decide whether to display the domain number in /proc */

/* Display the domain number in /proc */

int pci_proc_domain(struct pci_bus *bus)

{

	return 0;

	return pci_domain_nr(bus);

}



/* This header fixup will do the resource fixup for all devices as they are

drivers/pci/host/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -274,4 +274,15 @@ config PCIE_ARTPEC6 
	  Say Y here to enable PCIe controller support on Axis ARTPEC-6

	  SoCs.  This PCIe controller uses the DesignWare core.



config PCIE_ROCKCHIP

	bool "Rockchip PCIe controller"

	depends on ARCH_ROCKCHIP

	depends on OF

	depends on PCI_MSI_IRQ_DOMAIN

	select MFD_SYSCON

	help

	  Say Y here if you want internal PCI support on Rockchip SoC.

	  There is 1 internal PCIe port available to support GEN2 with

	  4 slots.



endmenu