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Commit 61d0c902 authored by Karthik Anantha Ram's avatar Karthik Anantha Ram
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ARM: dts: msm: Correct SVS clock level for IPE0 in Lahaina DT

The SVS clock rate for IPE0 is 450MHz as opposed to 475MHz.
This wrong entry resulted in clock being bumped to NOM instead
of SVS level.

CRs-Fixed: 2745429
Change-Id: I759cff68f3811d9f7c44d2fe99bbc0433895945a
parent b9d73ca1
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