Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 61d0c902 authored by Karthik Anantha Ram's avatar Karthik Anantha Ram
Browse files

ARM: dts: msm: Correct SVS clock level for IPE0 in Lahaina DT 

The SVS clock rate for IPE0 is 450MHz as opposed to 475MHz.
This wrong entry resulted in clock being bumped to NOM instead
of SVS level.

CRs-Fixed: 2745429
Change-Id: I759cff68f3811d9f7c44d2fe99bbc0433895945a
parent b9d73ca1

lahaina-camera.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1808,7 +1808,7 @@ 


		clock-rates =

			<0 0 0 300000000 0>,

			<0 0 0 475000000 0>,

			<0 0 0 450000000 0>,

			<0 0 0 525000000 0>,

			<0 0 0 700000000 0>,

			<0 0 0 700000000 0>;