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Commit 60818b86 authored by Thirupathi Reddy R's avatar Thirupathi Reddy R
Browse files

Merge commit '71a0fad8' into camera-kernel.lnx.4.0.r1-rel 



Change-Id: Ie92835a10b0d77eb385012916daac98367a1821d
Signed-off-by: default avatarThirupathi Reddy R <treddyr@qti.qualcomm.com>
parents ac2aea5b 71a0fad8

drivers/cam_cdm/cam_cdm_hw_core.c

+19 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/delay.h>
@@ -416,6 +416,17 @@ void cam_hw_cdm_dump_core_debug_registers(struct cam_hw_info *cdm_hw, 
	CAM_INFO(CAM_CDM, "curr BL base 0x%x AHB base 0x%x",

		dump_reg[0], dump_reg[1]);



	cam_cdm_read_hw_reg(cdm_hw,

		core->offsets->cmn_reg->wait_status, &dump_reg[0]);

	cam_cdm_read_hw_reg(cdm_hw,

		core->offsets->cmn_reg->comp_wait[0]->comp_wait_status,

		&dump_reg[1]);

	cam_cdm_read_hw_reg(cdm_hw,

		core->offsets->cmn_reg->comp_wait[1]->comp_wait_status,

		&dump_reg[2]);

	CAM_INFO(CAM_CDM, "wait status 0x%x comp wait status 0x%x: 0x%x",

		dump_reg[0], dump_reg[1], dump_reg[2]);



	cam_cdm_read_hw_reg(cdm_hw,

		core->offsets->cmn_reg->current_bl_len, &dump_reg[0]);

	CAM_INFO(CAM_CDM,
@@ -1138,7 +1149,7 @@ static void cam_hw_cdm_reset_cleanup( 
		test_bit(CAM_CDM_FLUSH_HW_STATUS, &core->cdm_status))

		flush_hw = true;



	if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status))

	if (test_bit(CAM_CDM_RESET_ERR_STATUS, &core->cdm_status))

		reset_err = true;



	for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) {
@@ -1488,6 +1499,8 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) 
			if (payload[i]->irq_data ==

				CAM_CDM_DBG_GEN_IRQ_USR_DATA)

				CAM_INFO(CAM_CDM, "Debug gen_irq received");



			atomic_inc(&cdm_core->bl_fifo[i].work_record);

		}



		CAM_DBG(CAM_CDM,
@@ -1514,7 +1527,6 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) 
			return IRQ_HANDLED;

		}



		atomic_inc(&cdm_core->bl_fifo[i].work_record);

		payload[i]->workq_scheduled_ts = ktime_get();



		work_status = queue_work(
@@ -1846,14 +1858,17 @@ int cam_hw_cdm_hang_detect( 
	uint32_t            handle)

{

	struct cam_cdm *cdm_core = NULL;

	struct cam_hw_soc_info *soc_info;

	int i, rc = -1;



	cdm_core = (struct cam_cdm *)cdm_hw->core_info;

	soc_info = &cdm_hw->soc_info;



	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++)

		if (atomic_read(&cdm_core->bl_fifo[i].work_record)) {

			CAM_WARN(CAM_CDM,

				"workqueue got delayed, work_record :%u",

				"workqueue got delayed for %s%u, work_record :%u",

				soc_info->label_name, soc_info->index,

				atomic_read(&cdm_core->bl_fifo[i].work_record));

			rc = 0;

			break;

drivers/cam_core/cam_context_utils.c

+93 −11
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/debugfs.h>
@@ -602,7 +602,7 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) 
	struct cam_hw_flush_args flush_args;

	struct list_head temp_list;

	struct cam_ctx_request *req;

	uint32_t i;

	uint32_t i, j;

	int rc = 0;

	bool free_req;
@@ -618,15 +618,31 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) 
	INIT_LIST_HEAD(&temp_list);

	spin_lock(&ctx->lock);

	list_splice_init(&ctx->pending_req_list, &temp_list);

	flush_args.num_req_pending = 0;

	list_for_each_entry(req, &temp_list, list) {

		flush_args.num_req_pending++;

	}

	spin_unlock(&ctx->lock);



	flush_args.flush_req_pending = kcalloc(flush_args.num_req_pending,

		sizeof(void *), GFP_KERNEL);

	if (!flush_args.flush_req_pending) {

		rc = -ENOMEM;

		CAM_ERR(CAM_CTXT,

			"[%s][%d] : Failed to malloc memory for flush_req_pending",

			ctx->dev_name, ctx->ctx_id);

		mutex_unlock(&ctx->sync_mutex);

		goto err;

	}



	if (cam_debug_ctx_req_list & ctx->dev_id)

		CAM_INFO(CAM_CTXT,

			"[%s][%d] : Moving all pending requests from pending_list to temp_list",

			ctx->dev_name, ctx->ctx_id);



	flush_args.num_req_pending = 0;

	flush_args.last_flush_req = ctx->last_flush_req;



	j = 0;

	while (true) {

		spin_lock(&ctx->lock);

		if (list_empty(&temp_list)) {
@@ -641,7 +657,7 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) 
		spin_unlock(&ctx->lock);

		req->flushed = 1;



		flush_args.flush_req_pending[flush_args.num_req_pending++] =

		flush_args.flush_req_pending[j++] =

			req->req_priv;



		free_req = false;
@@ -692,11 +708,31 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) 
	}

	mutex_unlock(&ctx->sync_mutex);



	kfree(flush_args.flush_req_pending);

	flush_args.flush_req_pending = NULL;



	if (ctx->hw_mgr_intf->hw_flush) {

		spin_lock(&ctx->lock);

		flush_args.num_req_active = 0;

		list_for_each_entry(req, &ctx->active_req_list, list) {

			flush_args.num_req_active++;

		}

		spin_unlock(&ctx->lock);



		flush_args.flush_req_active = kcalloc(flush_args.num_req_active,

			sizeof(void *), GFP_KERNEL);

		if (!flush_args.flush_req_active) {

			rc = -ENOMEM;

			CAM_ERR(CAM_CTXT,

				"[%s][%d] : Failed to malloc memory for flush_req_active",

				ctx->dev_name, ctx->ctx_id);

			goto err;

		}



		spin_lock(&ctx->lock);

		j = 0;

		list_for_each_entry(req, &ctx->active_req_list, list) {

			flush_args.flush_req_active[flush_args.num_req_active++]

			flush_args.flush_req_active[j++]

				= req->req_priv;

		}

		spin_unlock(&ctx->lock);
@@ -709,6 +745,9 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) 
		}

	}



	kfree(flush_args.flush_req_active);

	flush_args.flush_req_active = NULL;



	INIT_LIST_HEAD(&temp_list);

	spin_lock(&ctx->lock);

	list_splice_init(&ctx->active_req_list, &temp_list);
@@ -762,7 +801,8 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) 


	CAM_DBG(CAM_CTXT, "[%s] X: NRT flush ctx", ctx->dev_name);



	return 0;

err:

	return rc;

}



int32_t cam_context_flush_req_to_hw(struct cam_context *ctx,
@@ -782,6 +822,25 @@ int32_t cam_context_flush_req_to_hw(struct cam_context *ctx, 
	flush_args.num_req_active = 0;

	mutex_lock(&ctx->sync_mutex);

	spin_lock(&ctx->lock);

	list_for_each_entry(req, &ctx->pending_req_list, list) {

		if (req->request_id != cmd->req_id)

			continue;

		flush_args.num_req_pending++;

	}

	spin_unlock(&ctx->lock);



	flush_args.flush_req_pending = kcalloc(flush_args.num_req_pending,

		sizeof(void *), GFP_KERNEL);

	if (!flush_args.flush_req_pending) {

		rc = -ENOMEM;

		CAM_ERR(CAM_CTXT,

			"[%s][%d] : Failed to malloc memory for flush_req_pending",

			ctx->dev_name, ctx->ctx_id);

		goto err;

	}



	spin_lock(&ctx->lock);

	i = 0;

	list_for_each_entry(req, &ctx->pending_req_list, list) {

		if (req->request_id != cmd->req_id)

			continue;
@@ -794,24 +853,41 @@ int32_t cam_context_flush_req_to_hw(struct cam_context *ctx, 
		list_del_init(&req->list);

		req->flushed = 1;



		flush_args.flush_req_pending[flush_args.num_req_pending++] =

		flush_args.flush_req_pending[i++] =

			req->req_priv;

		break;

	}

	spin_unlock(&ctx->lock);

	mutex_unlock(&ctx->sync_mutex);



	if (ctx->hw_mgr_intf->hw_flush) {

		if (!flush_args.num_req_pending) {

			spin_lock(&ctx->lock);

			list_for_each_entry(req, &ctx->active_req_list, list) {

				if (req->request_id != cmd->req_id)

					continue;

				flush_args.num_req_active++;

			}

			spin_unlock(&ctx->lock);



			flush_args.flush_req_active = kcalloc(flush_args.num_req_active,

				sizeof(void *), GFP_KERNEL);

			if (!flush_args.flush_req_pending) {

				rc = -ENOMEM;

				CAM_ERR(CAM_CTXT,

					"[%s][%d] : Failed to malloc memory for flush_req_pending",

					ctx->dev_name, ctx->ctx_id);

				goto err;

			}



			spin_lock(&ctx->lock);

			i = 0;

			list_for_each_entry(req, &ctx->active_req_list, list) {

				if (req->request_id != cmd->req_id)

					continue;



				list_del_init(&req->list);



				flush_args.flush_req_active[

					flush_args.num_req_active++] =

				flush_args.flush_req_active[i++] =

					req->req_priv;

				break;

			}
@@ -823,6 +899,10 @@ int32_t cam_context_flush_req_to_hw(struct cam_context *ctx, 
			flush_args.flush_type = CAM_FLUSH_TYPE_REQ;

			ctx->hw_mgr_intf->hw_flush(

				ctx->hw_mgr_intf->hw_mgr_priv, &flush_args);

			kfree(flush_args.flush_req_pending);

			flush_args.flush_req_pending = NULL;

			kfree(flush_args.flush_req_active);

			flush_args.flush_req_active = NULL;

		}

	}
@@ -878,7 +958,9 @@ int32_t cam_context_flush_req_to_hw(struct cam_context *ctx, 
	}

	CAM_DBG(CAM_CTXT, "[%s] X: NRT flush req", ctx->dev_name);



	return 0;

err:

	mutex_unlock(&ctx->sync_mutex);

	return rc;

}



int32_t cam_context_flush_dev_to_hw(struct cam_context *ctx,

drivers/cam_core/cam_hw_mgr_intf.h

+3 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_HW_MGR_INTF_H_
@@ -289,9 +289,9 @@ struct cam_hw_config_args { 
struct cam_hw_flush_args {

	void                           *ctxt_to_hw_map;

	uint32_t                        num_req_pending;

	void                           *flush_req_pending[20];

	void                          **flush_req_pending;

	uint32_t                        num_req_active;

	void                           *flush_req_active[20];

	void                          **flush_req_active;

	enum flush_type_t               flush_type;

	uint32_t                        last_flush_req;

};

drivers/cam_cpas/cam_cpas_intf.c

+1 −6
Original line number Diff line number Diff line
@@ -161,19 +161,14 @@ bool cam_cpas_is_feature_supported(uint32_t flag, uint32_t hw_map, 
		if (soc_private->feature_info[i].feature == flag)

			break;



	if (i == soc_private->num_feature_info) {

		CAM_INFO(CAM_CPAS, "Feature not found, no of featues: %d",

			soc_private->num_feature_info);

	if (i == soc_private->num_feature_info)

		goto end;

	}



	if (soc_private->feature_info[i].type == CAM_CPAS_FEATURE_TYPE_DISABLE

		|| (soc_private->feature_info[i].type ==

		CAM_CPAS_FEATURE_TYPE_ENABLE)) {

		if ((soc_private->feature_info[i].hw_map & hw_map) == hw_map)

			supported = soc_private->feature_info[i].enable;

		else

			supported = !soc_private->feature_info[i].enable;

	} else {

		if (!fuse_val) {

			CAM_ERR(CAM_CPAS,

drivers/cam_cpas/cpas_top/cpastop_v570_200.h

+9 −8
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 */



#ifndef _CPASTOP_V570_200_H_
@@ -270,7 +270,7 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xA30, /* IFE_LINEAR_PRIORITYLUT_LOW */

			.value = 0x66665433,

			.value = 0x66666666,

		},

		.priority_lut_high = {

			.enable = true,
@@ -402,7 +402,7 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1430, /* IFE_RDI_WR_0_PRIORITYLUT_LOW */

			.value = 0x66665433,

			.value = 0x66666666,

		},

		.priority_lut_high = {

			.enable = true,
@@ -468,7 +468,7 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1A30, /* IFE_UBWC_STATS_0_PRIORITYLUT_LOW */

			.value = 0x66665433,

			.value = 0x66666666,

		},

		.priority_lut_high = {

			.enable = true,
@@ -595,14 +595,14 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2220, /* IPE0_RD_QOSGEN_SHAPING_LOW */

			.value = 0x13131313,

			.value = 0x12121212,

		},

		.qosgen_shaping_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2224, /* IPE0_RD_QOSGEN_SHAPING_HIGH */

			.value = 0x13131313,

			.value = 0x12121212,

		},

	},

	{
@@ -662,19 +662,20 @@ static struct cam_camnoc_specific 
			.offset = 0x2308, /* IPE1_BPS_RD_QOSGEN_MAINCTL */

			.value = 0x2,

		},

		//  TITAN_A_CAMNOC_cam_noc_amm_nrt_niu_0_qosgen_Shaping_Low

		.qosgen_shaping_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2320, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */

			.value = 0x24242424,

			.value = 0x23232323,

		},

		.qosgen_shaping_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2324, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */

			.value = 0x24242424,

			.value = 0x23232323,

		},

	},

	{