Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ac2aea5b authored by Thirupathi Reddy R's avatar Thirupathi Reddy R
Browse files

Revert "msm: camera: cpas: workaround fix for Shima-CAMNOC RDI latency buffer" 



This reverts commit b1f064f8.

Change-Id: I39ed14906fedc2cd6e7e87b0cf2652a1b08b246a
Signed-off-by: default avatarThirupathi Reddy R <treddyr@codeaurora.org>
parent 49e2245b

drivers/cam_cpas/cpas_top/cpastop_v570_200.h

+7 −8
Original line number Diff line number Diff line
@@ -270,7 +270,7 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xA30, /* IFE_LINEAR_PRIORITYLUT_LOW */

			.value = 0x66666666,

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,
@@ -402,7 +402,7 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1430, /* IFE_RDI_WR_0_PRIORITYLUT_LOW */

			.value = 0x66666666,

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,
@@ -468,7 +468,7 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1A30, /* IFE_UBWC_STATS_0_PRIORITYLUT_LOW */

			.value = 0x66666666,

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,
@@ -595,14 +595,14 @@ static struct cam_camnoc_specific 
			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2220, /* IPE0_RD_QOSGEN_SHAPING_LOW */

			.value = 0x12121212,

			.value = 0x13131313,

		},

		.qosgen_shaping_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2224, /* IPE0_RD_QOSGEN_SHAPING_HIGH */

			.value = 0x12121212,

			.value = 0x13131313,

		},

	},

	{
@@ -662,20 +662,19 @@ static struct cam_camnoc_specific 
			.offset = 0x2308, /* IPE1_BPS_RD_QOSGEN_MAINCTL */

			.value = 0x2,

		},

		//  TITAN_A_CAMNOC_cam_noc_amm_nrt_niu_0_qosgen_Shaping_Low  | 0xAC44320

		.qosgen_shaping_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2320, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */

			.value = 0x23232323,

			.value = 0x24242424,

		},

		.qosgen_shaping_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2324, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */

			.value = 0x23232323,

			.value = 0x24242424,

		},

	},

	{

drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c

+2 −12
Original line number Diff line number Diff line
@@ -1448,7 +1448,6 @@ static int cam_icp_update_clk_rate(struct cam_icp_hw_mgr *hw_mgr, 
	struct cam_hw_intf *icp_dev_intf = NULL;

	struct cam_hw_intf *dev_intf = NULL;

	struct cam_icp_clk_update_cmd clk_upd_cmd;

	uint32_t camera_hw_version;



	ipe0_dev_intf = hw_mgr->ipe0_dev_intf;

	ipe1_dev_intf = hw_mgr->ipe1_dev_intf;
@@ -1471,17 +1470,8 @@ static int cam_icp_update_clk_rate(struct cam_icp_hw_mgr *hw_mgr, 
		id = CAM_ICP_IPE_CMD_UPDATE_CLK;

	}



	cam_cpas_get_cpas_hw_version(&camera_hw_version);

	if ((camera_hw_version == 0x570200)&&

		(curr_clk_rate > ctx_data->clk_info.clk_rate[CAM_MAX_VOTE-1]) &&

		(ctx_data->icp_dev_acquire_info->dev_type != CAM_ICP_RES_TYPE_BPS)) {



		curr_clk_rate = ctx_data->clk_info.clk_rate[CAM_MAX_VOTE-1];

	}



	CAM_DBG(CAM_PERF, "clk_rate %u for dev_type %d, ver %x", curr_clk_rate,

		ctx_data->icp_dev_acquire_info->dev_type, camera_hw_version);



	CAM_DBG(CAM_PERF, "clk_rate %u for dev_type %d", curr_clk_rate,

		ctx_data->icp_dev_acquire_info->dev_type);

	clk_upd_cmd.curr_clk_rate = curr_clk_rate;

	clk_upd_cmd.ipe_bps_pc_enable = icp_hw_mgr.ipe_bps_pc_flag;

	clk_upd_cmd.clk_level = -1;