Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

- #clock-cells:	Should be <1>. The permitted clock-specifier values can be

		  found in include/dt-bindings/clock/bcm2835.h

- reg:		Specifies base physical address and size of the registers

- clocks:	The external oscillator clock phandle

- clocks:	phandles to the parent clocks used as input to the module, in

		  the following order:

		  - External oscillator

		  - DSI0 byte clock

		  - DSI0 DDR2 clock

		  - DSI0 DDR clock

		  - DSI1 byte clock

		  - DSI1 DDR2 clock

		  - DSI1 DDR clock

		  Only external oscillator is required.  The DSI clocks may

		  not be present, in which case their children will be

		  unusable.

Example:

* Samsung Exynos4415 Clock Controller

The Exynos4415 clock controller generates and supplies clock to various

consumer devices within the Exynos4415 SoC.

Required properties:

- compatible: should be one of the following:

  - "samsung,exynos4415-cmu" - for the main system clocks controller

    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).

  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory

    Controller (DMC) domain clock controller.

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume.

All available clocks are defined as preprocessor macros in

dt-bindings/clock/exynos4415.h header and can be used in device

tree sources.

Example 1: An example of a clock controller node is listed below.

	cmu: clock-controller@10030000 {

		compatible = "samsung,exynos4415-cmu";

		reg = <0x10030000 0x18000>;

		#clock-cells = <1>;

	};

	cmu-dmc: clock-controller@105C0000 {

		compatible = "samsung,exynos4415-cmu-dmc";

		reg = <0x105C0000 0x3000>;

		#clock-cells = <1>;

	};

* Hisilicon Hi3660 Clock Controller

The Hi3660 clock controller generates and supplies clock to various

controllers within the Hi3660 SoC.

Required Properties:

- compatible: the compatible should be one of the following strings to

	indicate the clock controller functionality.

	- "hisilicon,hi3660-crgctrl"

	- "hisilicon,hi3660-pctrl"

	- "hisilicon,hi3660-pmuctrl"

	- "hisilicon,hi3660-sctrl"

	- "hisilicon,hi3660-iomcu"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier

to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.

Examples:

	crg_ctrl: clock-controller@fff35000 {

		compatible = "hisilicon,hi3660-crgctrl", "syscon";

		reg = <0x0 0xfff35000 0x0 0x1000>;

		#clock-cells = <1>;

	};

	uart0: serial@fdf02000 {

		compatible = "arm,pl011", "arm,primecell";

		reg = <0x0 0xfdf02000 0x0 0x1000>;

		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,

			 <&crg_ctrl HI3660_PCLK>;

		clock-names = "uartclk", "apb_pclk";

		status = "disabled";

	};

Binding for IDT VersaClock5 programmable i2c clock generator.

The IDT VersaClock5 are programmable i2c clock generators providing

from 3 to 12 output clocks.

==I2C device node==

Required properties:

- compatible:	shall be one of "idt,5p49v5923" , "idt,5p49v5933".

- reg:		i2c device address, shall be 0x68 or 0x6a.

- #clock-cells:	from common clock binding; shall be set to 1.

- clocks:	from common clock binding; list of parent clock handles,

		- 5p49v5923: (required) either or both of XTAL or CLKIN

					reference clock.

		- 5p49v5933: (optional) property not present (internal

					Xtal used) or CLKIN reference

					clock.

- clock-names:	from common clock binding; clock input names, can be

		- 5p49v5923: (required) either or both of "xin", "clkin".

		- 5p49v5933: (optional) property not present or "clkin".

==Mapping between clock specifier and physical pins==

When referencing the provided clock in the DT using phandle and

clock specifier, the following mapping applies:

5P49V5923:

	0 -- OUT0_SEL_I2CB

	1 -- OUT1

	2 -- OUT2

5P49V5933:

	0 -- OUT0_SEL_I2CB

	1 -- OUT1

	2 -- OUT4

==Example==

/* 25MHz reference crystal */

ref25: ref25m {

	compatible = "fixed-clock";

	#clock-cells = <0>;

	clock-frequency = <25000000>;

};

i2c-master-node {

	/* IDT 5P49V5923 i2c clock generator */

	vc5: clock-generator@6a {

		compatible = "idt,5p49v5923";

		reg = <0x6a>;

		#clock-cells = <1>;

		/* Connect XIN input to 25MHz reference */

		clocks = <&ref25m>;

		clock-names = "xin";

	};

};

/* Consumer referencing the 5P49V5923 pin OUT1 */

consumer {

	...

	clocks = <&vc5 1>;

	...

}

- compatible : must be "marvell,armada-370-corediv-clock",

		       "marvell,armada-375-corediv-clock",

		       "marvell,armada-380-corediv-clock",

                       "marvell,mv98dx3236-corediv-clock",

- reg : must be the register address of Core Divider control register

- #clock-cells : from common clock binding; shall be set to 1