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Commit f59de563 authored by Chris Brandt's avatar Chris Brandt Committed by Stephen Boyd
Browse files

clk: renesas: mstp: ensure register writes complete 



When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.

Fixes: b6face40 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 6ff8ec98

drivers/clk/renesas/clk-mstp.c

+6 −0
Original line number Diff line number Diff line
@@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 
		value |= bitmask;

	cpg_mstp_write(group, value, group->smstpcr);



	if (!group->mstpsr) {

		/* dummy read to ensure write has completed */

		cpg_mstp_read(group, group->smstpcr);

		barrier_data(group->smstpcr);

	}



	spin_unlock_irqrestore(&group->lock, flags);



	if (!enable || !group->mstpsr)