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Commit 05c7c884 authored by Alisha Thapaliya's avatar Alisha Thapaliya
Browse files

Merge remote-tracking branch 'quic/display-kernel.lnx.1.0' into display-kernel.lnx.5.4 

* quic/display-kernel.lnx.1.0:
  disp: msm: sde: determine rotation capabilities from version
  disp: msm: sde: remove inline prefill properties
  disp: msm: sde: pre-downscale support for inline rotation v2
  disp: msm: sde: new formats added for true inline rotation v2
  disp: include: add pre-downscale fields to scaler config

Change-Id: I1427bf6b7add895fb226678935b21c3de84c5187
parents e5d0b998 1579af15

include/uapi/drm/sde_drm.h

+13 −0
Original line number Diff line number Diff line
@@ -230,6 +230,7 @@ struct sde_drm_de_v1 { 


#define SDE_DRM_QSEED3LITE

#define SDE_DRM_QSEED4

#define SDE_DRM_INLINE_PREDOWNSCALE



/**

 * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
@@ -263,6 +264,10 @@ struct sde_drm_de_v1 { 
 * @unsharp_mask_blend: Unsharp Blend Filter Ratio

 * @de_blend:          Ratio of two unsharp mask filters

 * @flags:             Scaler configuration flags

 * @pre_downscale_x_0  Pre-downscale ratio, x-direction, plane 0(Y/RGB)

 * @pre_downscale_x_1  Pre-downscale ratio, x-direction, plane 1(UV)

 * @pre_downscale_y_0  Pre-downscale ratio, y-direction, plane 0(Y/RGB)

 * @pre_downscale_y_1  Pre-downscale ratio, y-direction, plane 1(UV)

 */

struct sde_drm_scaler_v2 {

	/*
@@ -320,6 +325,14 @@ struct sde_drm_scaler_v2 { 
	uint32_t unsharp_mask_blend;

	uint32_t de_blend;

	uint32_t flags;



	/*

	 * Inline pre-downscale settings

	 */

	uint32_t pre_downscale_x_0;

	uint32_t pre_downscale_x_1;

	uint32_t pre_downscale_y_0;

	uint32_t pre_downscale_y_1;

};



/* Number of dest scalers supported */

msm/sde/sde_hw_catalog.c

+89 −81
Original line number Diff line number Diff line
@@ -69,9 +69,12 @@ 
#define MAX_DOWNSCALE_RATIO		4

#define SSPP_UNITY_SCALE		1



#define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR	11

#define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR	5

#define MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT	4

#define MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR	11

#define MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR	5

#define MAX_DOWNSCALE_RATIO_INROT_PD_RT_NUMERATOR	4

#define MAX_DOWNSCALE_RATIO_INROT_PD_RT_DENOMINATOR	1

#define MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT		4



#define MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT	1088



#define MAX_HORZ_DECIMATION		4
@@ -1255,23 +1258,33 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 


	sblk->format_list = sde_cfg->vig_formats;

	sblk->virt_format_list = sde_cfg->virt_vig_formats;

	if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) {

		set_bit(SDE_SSPP_TRUE_INLINE_ROT_V1, &sspp->features);



	if (sde_cfg->true_inline_rot_rev > 0) {

		set_bit(SDE_SSPP_TRUE_INLINE_ROT, &sspp->features);

		sblk->in_rot_format_list = sde_cfg->inline_rot_formats;

		sblk->in_rot_maxheight =

				MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT;

	}



	if (IS_SDE_INLINE_ROT_REV_200(sde_cfg->true_inline_rot_rev)) {

		set_bit(SDE_SSPP_PREDOWNSCALE, &sspp->features);

		sblk->in_rot_maxdwnscale_rt_num =

			sde_cfg->true_inline_dwnscale_rt_num;

				MAX_DOWNSCALE_RATIO_INROT_PD_RT_NUMERATOR;

		sblk->in_rot_maxdwnscale_rt_denom =

			sde_cfg->true_inline_dwnscale_rt_denom;

				MAX_DOWNSCALE_RATIO_INROT_PD_RT_DENOMINATOR;

		sblk->in_rot_maxdwnscale_nrt =

			sde_cfg->true_inline_dwnscale_nrt;

		sblk->in_rot_maxheight =

			MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT;

		sblk->in_rot_prefill_fudge_lines =

			sde_cfg->true_inline_prefill_fudge_lines;

		sblk->in_rot_prefill_lines_nv12 =

			sde_cfg->true_inline_prefill_lines_nv12;

		sblk->in_rot_prefill_lines =

			sde_cfg->true_inline_prefill_lines;

				MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT;

		sblk->in_rot_minpredwnscale_num =

				MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR;

		sblk->in_rot_minpredwnscale_denom =

				MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR;

	} else if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) {

		sblk->in_rot_maxdwnscale_rt_num =

				MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR;

		sblk->in_rot_maxdwnscale_rt_denom =

				MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR;

		sblk->in_rot_maxdwnscale_nrt =

				MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT;

	}



	if (sde_cfg->sc_cfg.has_sys_cache) {
@@ -2311,8 +2324,7 @@ static int sde_rot_parse_dt(struct device_node *np, 
	if (rc) {

		/*

		 * This is not a fatal error, system cache can be disabled

		 * in device tree, anyways recommendation is to have it

		 * enabled, so print an error but don't fail

		 * in device tree

		 */

		SDE_DEBUG("sys cache will be disabled rc:%d\n", rc);

		rc = 0;
@@ -4049,58 +4061,84 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg, 
	uint32_t virt_vig_list_size, in_rot_list_size = 0;

	uint32_t cursor_list_size = 0;

	uint32_t index = 0;

	const struct sde_format_extended *inline_fmt_tbl;





	/* cursor input formats */

	if (sde_cfg->has_cursor) {

		cursor_list_size = ARRAY_SIZE(cursor_formats);

		sde_cfg->cursor_formats = kcalloc(cursor_list_size,

			sizeof(struct sde_format_extended), GFP_KERNEL);

		if (!sde_cfg->cursor_formats) {

			rc = -ENOMEM;

			goto end;

			goto out;

		}

		index = sde_copy_formats(sde_cfg->cursor_formats,

			cursor_list_size, 0, cursor_formats,

			ARRAY_SIZE(cursor_formats));

	}



	/* DMA pipe input formats */

	dma_list_size = ARRAY_SIZE(plane_formats);

	vig_list_size = ARRAY_SIZE(plane_formats_vig);

	if (sde_cfg->has_vig_p010)

		vig_list_size += ARRAY_SIZE(p010_ubwc_formats);

	virt_vig_list_size = ARRAY_SIZE(plane_formats);

	wb2_list_size = ARRAY_SIZE(wb2_formats);



	if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev))

		in_rot_list_size = ARRAY_SIZE(true_inline_rot_v1_fmts);



	sde_cfg->dma_formats = kcalloc(dma_list_size,

		sizeof(struct sde_format_extended), GFP_KERNEL);

	if (!sde_cfg->dma_formats) {

		rc = -ENOMEM;

		goto end;

		goto free_cursor;

	}



	index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,

			0, plane_formats, ARRAY_SIZE(plane_formats));



	/* ViG pipe input formats */

	vig_list_size = ARRAY_SIZE(plane_formats_vig);

	if (sde_cfg->has_vig_p010)

		vig_list_size += ARRAY_SIZE(p010_ubwc_formats);

	sde_cfg->vig_formats = kcalloc(vig_list_size,

		sizeof(struct sde_format_extended), GFP_KERNEL);

	if (!sde_cfg->vig_formats) {

		rc = -ENOMEM;

		goto end;

		goto free_dma;

	}



	index = sde_copy_formats(sde_cfg->vig_formats, vig_list_size,

			0, plane_formats_vig, ARRAY_SIZE(plane_formats_vig));

	if (sde_cfg->has_vig_p010)

		index += sde_copy_formats(sde_cfg->vig_formats,

				vig_list_size, index, p010_ubwc_formats,

				ARRAY_SIZE(p010_ubwc_formats));



	/* Virtual ViG pipe input formats (all virt pipes use DMA formats) */

	virt_vig_list_size = ARRAY_SIZE(plane_formats);

	sde_cfg->virt_vig_formats = kcalloc(virt_vig_list_size,

		sizeof(struct sde_format_extended), GFP_KERNEL);

	if (!sde_cfg->virt_vig_formats) {

		rc = -ENOMEM;

		goto end;

		goto free_vig;

	}



	index = sde_copy_formats(sde_cfg->virt_vig_formats, virt_vig_list_size,

			0, plane_formats, ARRAY_SIZE(plane_formats));



	/* WB output formats */

	wb2_list_size = ARRAY_SIZE(wb2_formats);

	sde_cfg->wb_formats = kcalloc(wb2_list_size,

		sizeof(struct sde_format_extended), GFP_KERNEL);

	if (!sde_cfg->wb_formats) {

		SDE_ERROR("failed to allocate wb format list\n");

		rc = -ENOMEM;

		goto end;

		goto free_virt;

	}



	index = sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,

			0, wb2_formats, ARRAY_SIZE(wb2_formats));



	/* Rotation enabled input formats */

	if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) {

		inline_fmt_tbl = true_inline_rot_v1_fmts;

		in_rot_list_size = ARRAY_SIZE(true_inline_rot_v1_fmts);

	} else if (IS_SDE_INLINE_ROT_REV_200(sde_cfg->true_inline_rot_rev)) {

		inline_fmt_tbl = true_inline_rot_v2_fmts;

		in_rot_list_size = ARRAY_SIZE(true_inline_rot_v2_fmts);

	}



	if (in_rot_list_size) {
@@ -4109,30 +4147,27 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg, 
		if (!sde_cfg->inline_rot_formats) {

			SDE_ERROR("failed to alloc inline rot format list\n");

			rc = -ENOMEM;

			goto end;

		}

			goto free_wb;

		}



	index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,

		0, plane_formats, ARRAY_SIZE(plane_formats));



	index = sde_copy_formats(sde_cfg->vig_formats, vig_list_size,

		0, plane_formats_vig, ARRAY_SIZE(plane_formats_vig));

	if (sde_cfg->has_vig_p010)

		index += sde_copy_formats(sde_cfg->vig_formats,

			vig_list_size, index, p010_ubwc_formats,

			ARRAY_SIZE(p010_ubwc_formats));

		index = sde_copy_formats(sde_cfg->inline_rot_formats,

			in_rot_list_size, 0, inline_fmt_tbl, in_rot_list_size);

	}



	index = sde_copy_formats(sde_cfg->virt_vig_formats, virt_vig_list_size,

		0, plane_formats, ARRAY_SIZE(plane_formats));

	return 0;



	index = sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,

		0, wb2_formats, ARRAY_SIZE(wb2_formats));

	if (in_rot_list_size)

		index = sde_copy_formats(sde_cfg->inline_rot_formats,

			in_rot_list_size, 0, true_inline_rot_v1_fmts,

			ARRAY_SIZE(true_inline_rot_v1_fmts));

end:

free_wb:

	kfree(sde_cfg->wb_formats);

free_virt:

	kfree(sde_cfg->virt_vig_formats);

free_vig:

	kfree(sde_cfg->vig_formats);

free_dma:

	kfree(sde_cfg->dma_formats);

free_cursor:

	if (sde_cfg->has_cursor)

		kfree(sde_cfg->cursor_formats);

out:

	return rc;

}
@@ -4286,15 +4321,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);

		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;

		sde_cfg->inline_disable_const_clr = true;

	} else if (IS_SAIPAN_TARGET(hw_rev)) {
@@ -4317,15 +4343,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);

		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->inline_disable_const_clr = true;

	} else if (IS_SDMTRINKET_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;
@@ -4372,16 +4389,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_hdr_plus = true;

		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);

		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;

		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else {

msm/sde/sde_hw_catalog.h

+13 −22
Original line number Diff line number Diff line
@@ -94,8 +94,13 @@ 
 * True inline rotation supported versions

 */

#define SDE_INLINE_ROT_VERSION_1_0_0	0x100

#define SDE_INLINE_ROT_VERSION_2_0_0	0x200



#define IS_SDE_INLINE_ROT_REV_100(rev) \

	((rev) == SDE_INLINE_ROT_VERSION_1_0_0)

#define IS_SDE_INLINE_ROT_REV_200(rev) \

	((rev) == SDE_INLINE_ROT_VERSION_2_0_0)





/*

 * UIDLE supported versions
@@ -211,7 +216,8 @@ enum { 
 * @SDE_SSPP_SEC_UI_ALLOWED   Allows secure-ui layers

 * @SDE_SSPP_BLOCK_SEC_UI    Blocks secure-ui layers

 * @SDE_SSPP_SCALER_QSEED3LITE Qseed3lite algorithm support

 * @SDE_SSPP_TRUE_INLINE_ROT_V1, Support of SSPP true inline rotation v1

 * @SDE_SSPP_TRUE_INLINE_ROT Support of SSPP true inline rotation v1

 * @SDE_SSPP_PREDOWNSCALE    Support pre-downscale X-direction by 2 for inline

 * @SDE_SSPP_INLINE_CONST_CLR Inline rotation requires const clr disabled

 * @SDE_SSPP_MAX             maximum value

 */
@@ -240,7 +246,8 @@ enum { 
	SDE_SSPP_SEC_UI_ALLOWED,

	SDE_SSPP_BLOCK_SEC_UI,

	SDE_SSPP_SCALER_QSEED3LITE,

	SDE_SSPP_TRUE_INLINE_ROT_V1,

	SDE_SSPP_TRUE_INLINE_ROT,

	SDE_SSPP_PREDOWNSCALE,

	SDE_SSPP_INLINE_CONST_CLR,

	SDE_SSPP_MAX

};
@@ -617,10 +624,9 @@ struct sde_qos_lut_tbl { 
 * @in_rot_maxdwnscale_rt_denom: max downscale ratio for inline rotation

 *                                 rt clients - denominator

 * @in_rot_maxdwnscale_nrt: max downscale ratio for inline rotation nrt clients

 * @in_rot_minpredwnscale_num: min downscale ratio to enable pre-downscale

 * @in_rot_minpredwnscale_denom: min downscale ratio to enable pre-downscale

 * @in_rot_maxheight: max pre rotated height for inline rotation

 * @in_rot_prefill_fudge_lines: prefill fudge lines for inline rotation

 * @in_rot_prefill_lines_mv12: prefill lines for nv12 format inline rotation

 * @in_rot_prefill_lines: prefill lines for inline rotation

 * @llcc_scid: scid for the system cache

 * @llcc_slice size: slice size of the system cache

 */
@@ -656,10 +662,9 @@ struct sde_sspp_sub_blks { 
	u32 in_rot_maxdwnscale_rt_num;

	u32 in_rot_maxdwnscale_rt_denom;

	u32 in_rot_maxdwnscale_nrt;

	u32 in_rot_minpredwnscale_num;

	u32 in_rot_minpredwnscale_denom;

	u32 in_rot_maxheight;

	u32 in_rot_prefill_fudge_lines;

	u32 in_rot_prefill_lines_nv12;

	u32 in_rot_prefill_lines;

	int llcc_scid;

	size_t llcc_slice_size;

};
@@ -1266,14 +1271,6 @@ struct sde_limit_cfg { 
 * @vbif_qos_nlvl      number of vbif QoS priority level

 * @ts_prefill_rev     prefill traffic shaper feature revision

 * @true_inline_rot_rev	inline rotator feature revision

 * @true_inline_dwnscale_rt_num    true inline rotator downscale ratio for rt

 *                                       - numerator

 * @true_inline_dwnscale_rt_denom    true inline rot downscale ratio for rt

 *                                       - denominator

 * @true_inline_dwnscale_nrt    true inline rotator downscale ratio for nrt

 * @true_inline_prefill_fudge_lines    true inline rotator prefill fudge lines

 * @true_inline_prefill_lines_nv12    true inline prefill lines for nv12 format

 * @true_inline_prefill_lines    true inline prefill lines

 * @macrotile_mode     UBWC parameter for macro tile channel distribution

 * @pipe_order_type    indicate if it is required to specify pipe order

 * @delay_prg_fetch_start indicates if throttling the fetch start is required
@@ -1331,12 +1328,6 @@ struct sde_mdss_cfg { 
	u32 vbif_qos_nlvl;

	u32 ts_prefill_rev;

	u32 true_inline_rot_rev;

	u32 true_inline_dwnscale_rt_num;

	u32 true_inline_dwnscale_rt_denom;

	u32 true_inline_dwnscale_nrt;

	u32 true_inline_prefill_fudge_lines;

	u32 true_inline_prefill_lines_nv12;

	u32 true_inline_prefill_lines;

	u32 macrotile_mode;

	u32 pipe_order_type;

	bool delay_prg_fetch_start;

msm/sde/sde_hw_catalog_format.h

+12 −4
Original line number Diff line number Diff line
@@ -53,6 +53,8 @@ 


#define P010_FMTS	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_DX}



#define P010_UBWC_FMTS	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_DX | \

		DRM_FORMAT_MOD_QCOM_COMPRESSED}



static const struct sde_format_extended plane_formats[] = {

	RGB_FMTS,
@@ -146,13 +148,19 @@ static const struct sde_format_extended wb2_formats[] = { 
};



static const struct sde_format_extended p010_ubwc_formats[] = {

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_DX |

		DRM_FORMAT_MOD_QCOM_COMPRESSED},

	P010_UBWC_FMTS,

};



static const struct sde_format_extended true_inline_rot_v1_fmts[] = {

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED |

		DRM_FORMAT_MOD_QCOM_DX | DRM_FORMAT_MOD_QCOM_TIGHT}, /* tp10 */

	TP10_UBWC_FMTS,

	{0, 0},

};



static const struct sde_format_extended true_inline_rot_v2_fmts[] = {

	{DRM_FORMAT_ABGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	TP10_UBWC_FMTS,

	P010_UBWC_FMTS,

	{0, 0},

};

msm/sde/sde_hw_sspp.c

+21 −1
Original line number Diff line number Diff line
@@ -67,7 +67,8 @@ 
#define SSPP_SRC_CONSTANT_COLOR            0x3c

#define SSPP_EXCL_REC_CTL                  0x40

#define SSPP_UBWC_STATIC_CTRL              0x44

#define SSPP_FETCH_CONFIG                  0x048

#define SSPP_FETCH_CONFIG                  0x48

#define SSPP_PRE_DOWN_SCALE                0x50

#define SSPP_DANGER_LUT                    0x60

#define SSPP_SAFE_LUT                      0x64

#define SSPP_CREQ_LUT                      0x68
@@ -596,6 +597,22 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, 
		ctx->cap->sblk->scaler_blk.version, idx, sspp->layout.format);

}



static void sde_hw_sspp_setup_pre_downscale(struct sde_hw_pipe *ctx,

		struct sde_hw_inline_pre_downscale_cfg *pre_down)

{

	u32 idx, val;



	if (!ctx || !pre_down || _sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))

		return;



	val = pre_down->pre_downscale_x_0 |

			(pre_down->pre_downscale_x_1 << 4) |

			(pre_down->pre_downscale_y_0 << 8) |

			(pre_down->pre_downscale_y_1 << 12);



	SDE_REG_WRITE(&ctx->hw, SSPP_PRE_DOWN_SCALE + idx, val);

}



static u32 _sde_hw_sspp_get_scaler3_ver(struct sde_hw_pipe *ctx)

{

	u32 idx;
@@ -1242,6 +1259,9 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
			c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;

	}



	if (test_bit(SDE_SSPP_PREDOWNSCALE, &features))

		c->ops.setup_pre_downscale = sde_hw_sspp_setup_pre_downscale;



	if (test_bit(SDE_PERF_SSPP_SYS_CACHE, &perf_features))

		c->ops.setup_sys_cache = sde_hw_sspp_setup_sys_cache;