arm64: mm: Workaround Cortex-A77 erratum 1542418 on ASID rollover

On affected Cortex-A77 cores, software relying on the
prefetch-speculation-protection instead of explicit synchronisation may
fetch a stale instruction from a CPU-specific cache. This violates the
ordering rules for instruction fetches.

This can only happen when the CPU correctly predicts the modified branch
based on a previous ASID/VMID. The workaround is to prevent these
predictions by selecting 60 ASIDs before an ASID is reused.

Add this logic as a workaround in the asid-alloctor's per-cpu rollover
path. When the first asid of the new generation is about to be used,
select 60 different ASIDs before we do the TLB maintenance.

Change-Id: If51a1bfc56679161eab3a79c535f92f7a0ab0882
Signed-off-by: James Morse <james.morse@arm.com>
[suzuki.poulose@arm.com: Added/modified commentary ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Patch-mainline: linux-arm-kernel @ 11/14/19, 14:59
[sramana@codeaurora.org: Resolve merge conflicts. Always return false
on CNP feature check as its not supported yet on this kernel ]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>