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Commit fe43b6c3 authored by James Morse's avatar James Morse Committed by Srinivas Ramana
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arm64: mm: Workaround Cortex-A77 erratum 1542418 on ASID rollover 



On affected Cortex-A77 cores, software relying on the
prefetch-speculation-protection instead of explicit synchronisation may
fetch a stale instruction from a CPU-specific cache. This violates the
ordering rules for instruction fetches.

This can only happen when the CPU correctly predicts the modified branch
based on a previous ASID/VMID. The workaround is to prevent these
predictions by selecting 60 ASIDs before an ASID is reused.

Add this logic as a workaround in the asid-alloctor's per-cpu rollover
path. When the first asid of the new generation is about to be used,
select 60 different ASIDs before we do the TLB maintenance.

Change-Id: If51a1bfc56679161eab3a79c535f92f7a0ab0882
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
[suzuki.poulose@arm.com: Added/modified commentary ]
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Patch-mainline: linux-arm-kernel @ 11/14/19, 14:59
[sramana@codeaurora.org: Resolve merge conflicts. Always return false
on CNP feature check as its not supported yet on this kernel ]
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent b4a6b5b1

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ stable kernels. 
| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

| ARM            | Cortex-A77      | #1542418        | ARM64_ERRATUM_1542418       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -524,6 +524,22 @@ config ARM64_ERRATUM_1463225 


	  If unsure, say Y.



config ARM64_ERRATUM_1542418

	bool "Cortex-A77: The core might fetch a stale instuction, violating the ordering of instruction fetches"

	default y

	help

	  This option adds a workaround for Arm Cortex-A77 erratum 1542418.



	  On the affected Cortex-A77 cores (r0p0 and r1p0), software relying

	  on the prefetch-speculation-protection instead of explicit

	  synchronisation may fetch a stale instruction from a CPU-specific

	  cache. This violates the ordering rules for instruction fetches.



	  Work around the erratum by ensuring that 60 ASIDs are selected

	  before any ASID is reused.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −2
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 
#define ARM64_WORKAROUND_1463225		33

#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1188873		35



#define ARM64_NCAPS				36

#define ARM64_WORKAROUND_1542418		36

#define ARM64_NCAPS				37



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cpufeature.h

+5 −0
Original line number Diff line number Diff line
@@ -509,6 +509,11 @@ static inline bool system_supports_sve(void) 
		cpus_have_const_cap(ARM64_SVE);

}



static inline bool system_supports_cnp(void)

{

	return false;

}



#define ARM64_SSBD_UNKNOWN		-1

#define ARM64_SSBD_FORCE_DISABLE	0

#define ARM64_SSBD_KERNEL		1

arch/arm64/kernel/cpu_errata.c

+7 −0
Original line number Diff line number Diff line
@@ -875,6 +875,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),

		.matches = needs_tx2_tvm_workaround,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1542418

	{

		.desc = "ARM erratum 1542418",

		.capability = ARM64_WORKAROUND_1542418,

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),

	},

#endif

	{

	}