data-kernel: EMAC: Fix clk rates and bus BW votes in suspend

Vote for zero bus BW for AXI/AHB clocks
Set clock rate to zero for RGMII TX clock.

CRs-Fixed: 2280671
Change-Id: I86c496bc4d681dbc7d921466b6b63dd513d9196e
Acked-by: Rahul Kawadgave <rahulak@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>