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Commit be72cb4a authored by Hareesh Gundu's avatar Hareesh Gundu Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Add a feature ADRENO_PERFCTRL_RETAIN 



Add a ADRENO_PERFCTRL_RETAIN feature to enable it
target specific. This feature will allows to retain
RBBM perf control enable setting value across power
collapse interval. This is needed to start counting
perf counter after the IFPC.

Also enable this feature for A608 GPU.

Change-Id: I79ba7cfa5afb7d16745673eb740b9cddc229d091
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 6148b2db

drivers/gpu/msm/adreno-gpulist.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -461,7 +461,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.patchid = ANY_ID,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC,

			ADRENO_IFPC | ADRENO_PERFCTRL_RETAIN,

		.sqefw_name = "a630_sqe.fw",

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a608_zap",

		.zap_name = "a608_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gpudev = &adreno_a6xx_gpudev,

drivers/gpu/msm/adreno.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -115,6 +115,8 @@ 
#define ADRENO_MIN_VOLT BIT(15)

#define ADRENO_MIN_VOLT BIT(15)

/* The core supports IO-coherent memory */

/* The core supports IO-coherent memory */

#define ADRENO_IOCOHERENT BIT(16)

#define ADRENO_IOCOHERENT BIT(16)

/* To retain RBBM perfcntl enable setting in IFPC */

#define ADRENO_PERFCTRL_RETAIN BIT(17)

/*

/*

 * The GMU supports Adaptive Clock Distribution (ACD)

 * The GMU supports Adaptive Clock Distribution (ACD)

 * for droop mitigation

 * for droop mitigation

drivers/gpu/msm/adreno_a6xx.c

+42 −3
Original line number Original line Diff line number Diff line
@@ -461,6 +461,10 @@ static struct reg_list_pair a615_pwrup_reglist[] = { 
	{ A6XX_UCHE_GBIF_GX_CONFIG, 0x0 },

	{ A6XX_UCHE_GBIF_GX_CONFIG, 0x0 },

};

};





static struct reg_list_pair a6xx_ifpc_perfctr_reglist[] = {

	{ A6XX_RBBM_PERFCTR_CNTL, 0x0 },

};



static void _update_always_on_regs(struct adreno_device *adreno_dev)

static void _update_always_on_regs(struct adreno_device *adreno_dev)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
@@ -726,7 +730,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
		+ sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist,

		+ sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist,

		sizeof(a6xx_pwrup_reglist));

		sizeof(a6xx_pwrup_reglist));





	if (adreno_is_a615_family(adreno_dev) || adreno_is_a608(adreno_dev)) {

	if (adreno_is_a615_family(adreno_dev)) {

		for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) {

		for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) {

			r = &a615_pwrup_reglist[i];

			r = &a615_pwrup_reglist[i];

			kgsl_regread(KGSL_DEVICE(adreno_dev),

			kgsl_regread(KGSL_DEVICE(adreno_dev),
@@ -740,6 +744,22 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 




		lock->list_length += sizeof(a615_pwrup_reglist) >> 2;

		lock->list_length += sizeof(a615_pwrup_reglist) >> 2;

	}

	}



	if (ADRENO_FEATURE(adreno_dev, ADRENO_PERFCTRL_RETAIN)) {

		for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_perfctr_reglist); i++) {

			r = &a6xx_ifpc_perfctr_reglist[i];

			kgsl_regread(KGSL_DEVICE(adreno_dev),

				r->offset, &r->val);

		}



		memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock)

				+ sizeof(a6xx_ifpc_pwrup_reglist)

				+ sizeof(a6xx_pwrup_reglist),

				a6xx_ifpc_perfctr_reglist,

				sizeof(a6xx_ifpc_perfctr_reglist));



		lock->list_length += sizeof(a6xx_ifpc_perfctr_reglist) >> 2;

	}

}

}





/*

/*
@@ -2913,9 +2933,28 @@ static int a6xx_perfcounter_update(struct adreno_device *adreno_dev, 
	for (i = 0; i < lock->list_length >> 1; i++)

	for (i = 0; i < lock->list_length >> 1; i++)

		if (reg_pair[i].offset == reg->select)

		if (reg_pair[i].offset == reg->select)

			break;

			break;

	/*

	 * If the perfcounter selct register is not present overwrite last entry

	 * with new entry and add RBBM perf counter enable at the end.

	 */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_PERFCTRL_RETAIN) &&

			(i == lock->list_length >> 1)) {

		reg_pair[i-1].offset = reg->select;

		reg_pair[i-1].val = reg->countable;





		/* Enable perf counter after performance counter selections */

		reg_pair[i].offset = A6XX_RBBM_PERFCTR_CNTL;

		reg_pair[i].val = 1;



	} else {

		/*

		 * If perf counter select register is already present in reglist

		 * just update list without adding the RBBM perfcontrol enable.

		 */

		reg_pair[i].offset = reg->select;

		reg_pair[i].offset = reg->select;

		reg_pair[i].val = reg->countable;

		reg_pair[i].val = reg->countable;

	}



	if (i == lock->list_length >> 1)

	if (i == lock->list_length >> 1)

		lock->list_length += 2;

		lock->list_length += 2;