Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a47c6336 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: qcom: update NPU on Kona for auto pil and SSR support"

parents 8476fdfe 5b63397d
Loading
Loading
Loading
Loading
+7 −4
Original line number Diff line number Diff line
@@ -10,12 +10,15 @@
		reg = <0x9900000 0x20000>,
			<0x99F0000 0x10000>,
			<0x9800000 0x100000>,
			<0x9980000 0x10000>,
			<0x17c00000 0x10000>;
		reg-names = "tcm", "core", "qdsp", "apss_shared";
		interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
		reg-names = "tcm", "core", "qdsp", "cc", "apss_shared";
		interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";
				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
					"general_irq";
		iommus = <&apps_smmu 0x1081 0x400>, <&apps_smmu 0x1082 0x400>,
			<&apps_smmu 0x10A1 0x400>, <&apps_smmu 0x10A2 0x400>;

+4 −4
Original line number Diff line number Diff line
@@ -56,13 +56,13 @@ enum npu_power_level {
};

#define NPU_ERR(fmt, args...)                            \
	pr_err("NPU_ERR: %s: %d " fmt "\n", __func__,  __LINE__, ##args)
	pr_err("NPU_ERR: %s: %d " fmt, __func__,  __LINE__, ##args)
#define NPU_WARN(fmt, args...)                           \
	pr_warn("NPU_WARN: %s: %d " fmt "\n", __func__,  __LINE__, ##args)
	pr_warn("NPU_WARN: %s: %d " fmt, __func__,  __LINE__, ##args)
#define NPU_INFO(fmt, args...)                           \
	pr_info("NPU_INFO: %s: %d " fmt "\n", __func__,  __LINE__, ##args)
	pr_info("NPU_INFO: %s: %d " fmt, __func__,  __LINE__, ##args)
#define NPU_DBG(fmt, args...)                           \
	pr_debug("NPU_DBG: %s: %d " fmt "\n", __func__,  __LINE__, ##args)
	pr_debug("NPU_DBG: %s: %d " fmt, __func__,  __LINE__, ##args)

/* -------------------------------------------------------------------------
 * Data Structures
+19 −2
Original line number Diff line number Diff line
@@ -314,7 +314,6 @@ int npu_enable_core_power(struct npu_device *npu_dev)
void npu_disable_core_power(struct npu_device *npu_dev)
{
	struct npu_pwrctrl *pwr = &npu_dev->pwrctrl;
	struct npu_thermalctrl *thermalctrl = &npu_dev->thermalctrl;

	if (!pwr->pwr_vote_num)
		return;
@@ -322,7 +321,7 @@ void npu_disable_core_power(struct npu_device *npu_dev)
	if (!pwr->pwr_vote_num) {
		npu_disable_core_clocks(npu_dev);
		npu_disable_regulators(npu_dev);
		pwr->active_pwrlevel = thermalctrl->pwr_level;
		pwr->active_pwrlevel = pwr->default_pwrlevel;
		pwr->uc_pwrlevel = pwr->max_pwrlevel;
		pwr->cdsprm_pwrlevel = pwr->max_pwrlevel;
		NPU_DBG("setting back to power level=%d\n",
@@ -434,6 +433,24 @@ static int npu_set_power_level(struct npu_device *npu_dev, bool notify_cxlimit)
	pwr_level_idx = npu_power_level_to_index(npu_dev, pwr_level_to_set);
	pwrlevel = &npu_dev->pwrctrl.pwrlevels[pwr_level_idx];

	ret = npu_host_notify_fw_pwr_state(npu_dev, pwr_level_to_set, false);
	/*
	 * if new power level is lower than current power level,
	 * ignore fw notification failure, and apply the new power level.
	 * otherwise remain the current power level.
	 */

	if (ret) {
		NPU_WARN("notify fw new power level [%d] failed\n",
			pwr_level_to_set);
		if (pwr->active_pwrlevel < pwr_level_to_set) {
			NPU_WARN("remain current power level [%d]\n",
				pwr->active_pwrlevel);
			return 0;
		}

		ret = 0;
	}
	for (i = 0; i < npu_dev->core_clk_num; i++) {
		if (npu_is_exclude_rate_clock(
			npu_dev->core_clks[i].clk_name))
+6 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@
#define FW_CTRL_STATUS_EXECUTING_ACO_BIT        5
#define FW_CTRL_STATUS_SHUTDOWN_DONE_BIT        12
#define FW_CTRL_STATUS_STACK_CORRUPT_BIT        13
#define FW_CTRL_STATUS_PWR_NOTIFY_DONE_BIT      16
#define FW_CTRL_STATUS_PWR_NOTIFY_ERR_BIT       17

/* 32 bit values of the bit fields above */
#define FW_CTRL_STATUS_IPC_READY_VAL    (1 << FW_CTRL_STATUS_IPC_READY_BIT)
@@ -60,6 +62,10 @@
			(1 << FW_CTRL_STATUS_SHUTDOWN_DONE_BIT)
#define FW_CTRL_STATUS_STACK_CORRUPT_VAL \
			(1 << FW_CTRL_STATUS_STACK_CORRUPT_BIT)
#define FW_CTRL_STATUS_PWR_NOTIFY_DONE_VAL \
				(1 << FW_CTRL_STATUS_PWR_NOTIFY_DONE_BIT)
#define FW_CTRL_STATUS_PWR_NOTIFY_ERR_VAL \
				(1 << FW_CTRL_STATUS_PWR_NOTIFY_ERR_BIT)

/* NPU HOST Control/Status Register */
/* bit fields definitions in CTRL STATUS REG */
+27 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@
#define NPU_IPC_CMD_LOAD_V2             0x00000009
/* ipc_cmd_execute_packet_v2 */
#define NPU_IPC_CMD_EXECUTE_V2          0x0000000A
/* npu_ipc_cmd_notify_pwr_packet_t */
#define NPU_IPC_CMD_NOTIFY_PWR          0x0000000B

/* Messages sent **from** NPU */
/* IPC Message Response -- uint32_t */
@@ -48,6 +50,8 @@
#define NPU_IPC_MSG_LOOPBACK_DONE       0x00010005
/* ipc_msg_execute_pkt_v2 */
#define NPU_IPC_MSG_EXECUTE_V2_DONE     0x00010006
/* struct ipc_msg_notify_pwr_pkt */
#define NPU_IPC_MSG_NOTIFY_PWR_DONE     0x00010007

/* Logging message size */
/* Number 32-bit elements for the maximum log message size */
@@ -410,4 +414,27 @@ struct ipc_cmd_shutdown_pkt {
	uint32_t shutdown_flags;
};

/*
 * Power state notification packet definition
 */
enum npu_pwr_notification_type {
	NPU_POWER_PRE_NOTIFY   = 0x00000001,
	NPU_POWER_POST_NOTIFY  = 0x00000002,
};

struct ipc_cmd_notify_pwr_pkt {
	struct ipc_cmd_header_pkt header;
	/* enum npu_power_level */
	uint32_t pwr_level;
	/* enum npu_pwr_notification_type */
	uint32_t notify_type;
};

/*
 * NOTIFY_PWR cmd response packet definition
 */
struct ipc_msg_notify_pwr_pkt {
	struct ipc_msg_header_pkt header;
};

#endif /* NPU_HOST_IPC_H */
Loading