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Commit 5b63397d authored by Jilai Wang's avatar Jilai Wang
Browse files

ARM: dts: qcom: update NPU on Kona for auto pil and SSR support 



This change is to add a new memory region for NPU_CC register
space and a new irq for general interrupt which will be used by
auto pil to control BRINGUP/SHUTDOWN interrupts generated by NPU
Q6. It also updates error_irq type which is used by NPU SSR.

Change-Id: Id0bc27e34252ba44fc248319d4af32d58a89668f
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 15f82b74

arch/arm64/boot/dts/qcom/kona-npu.dtsi

+7 −4
Original line number Diff line number Diff line
@@ -10,12 +10,15 @@ 
		reg = <0x9900000 0x20000>,

			<0x99F0000 0x10000>,

			<0x9800000 0x100000>,

			<0x9980000 0x10000>,

			<0x17c00000 0x10000>;

		reg-names = "tcm", "core", "qdsp", "apss_shared";

		interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,

		reg-names = "tcm", "core", "qdsp", "cc", "apss_shared";

		interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";

				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",

					"general_irq";

		iommus = <&apps_smmu 0x1081 0x400>, <&apps_smmu 0x1082 0x400>,

			<&apps_smmu 0x10A1 0x400>, <&apps_smmu 0x10A2 0x400>;