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Commit 8476fdfe authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: pcie: add LTSSM definitions"

parents 22b95ff5 ea1a4ad4

arch/arm64/boot/dts/qcom/kona-pcie.dtsi

+3 −6
Original line number Diff line number Diff line
@@ -71,14 +71,13 @@ 
			<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>,

			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;

		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",

				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",

				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_phy_aux_clk", "pcie_ddrss_sf_tbu_clk";

				"pcie_ddrss_sf_tbu_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;
@@ -311,14 +310,13 @@ 
			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>,

			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;

		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",

				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",

				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",

				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_phy_aux_clk", "pcie_ddrss_sf_tbu_clk";

				"pcie_ddrss_sf_tbu_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;
@@ -590,14 +588,13 @@ 
			<&clock_gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE2_PHY_REFGEN_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>,

			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;

		clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src",

				"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",

				"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",

				"pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_phy_aux_clk", "pcie_ddrss_sf_tbu_clk";

				"pcie_ddrss_sf_tbu_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;

drivers/pci/controller/pci-msm.c

+85 −2
Original line number Diff line number Diff line
@@ -148,6 +148,8 @@ 
#define MSM_PCIE_IOMMU_ATOMIC BIT(3)

#define MSM_PCIE_IOMMU_FORCE_COHERENT BIT(4)



#define MSM_PCIE_LTSSM_MASK (0x3f)



#define PHY_READY_TIMEOUT_COUNT (10)

#define XMLH_LINK_UP (0x400)

#define MAX_PROP_SIZE (32)
@@ -326,6 +328,87 @@ enum msm_pcie_boot_option { 
	MSM_PCIE_NO_WAKE_ENUMERATION = BIT(1)

};



enum msm_pcie_ltssm {

	MSM_PCIE_LTSSM_DETECT_QUIET = 0x00,

	MSM_PCIE_LTSSM_DETECT_ACT = 0x01,

	MSM_PCIE_LTSSM_POLL_ACTIVE = 0x02,

	MSM_PCIE_LTSSM_POLL_COMPLIANCE = 0x03,

	MSM_PCIE_LTSSM_POLL_CONFIG = 0x04,

	MSM_PCIE_LTSSM_PRE_DETECT_QUIET = 0x05,

	MSM_PCIE_LTSSM_DETECT_WAIT = 0x06,

	MSM_PCIE_LTSSM_CFG_LINKWD_START = 0x07,

	MSM_PCIE_LTSSM_CFG_LINKWD_ACEPT = 0x08,

	MSM_PCIE_LTSSM_CFG_LANENUM_WAIT = 0x09,

	MSM_PCIE_LTSSM_CFG_LANENUM_ACEPT = 0x0a,

	MSM_PCIE_LTSSM_CFG_COMPLETE = 0x0b,

	MSM_PCIE_LTSSM_CFG_IDLE = 0x0c,

	MSM_PCIE_LTSSM_RCVRY_LOCK = 0x0d,

	MSM_PCIE_LTSSM_RCVRY_SPEED = 0x0e,

	MSM_PCIE_LTSSM_RCVRY_RCVRCFG = 0x0f,

	MSM_PCIE_LTSSM_RCVRY_IDLE = 0x10,

	MSM_PCIE_LTSSM_RCVRY_EQ0 = 0x20,

	MSM_PCIE_LTSSM_RCVRY_EQ1 = 0x21,

	MSM_PCIE_LTSSM_RCVRY_EQ2 = 0x22,

	MSM_PCIE_LTSSM_RCVRY_EQ3 = 0x23,

	MSM_PCIE_LTSSM_L0 = 0x11,

	MSM_PCIE_LTSSM_L0S = 0x12,

	MSM_PCIE_LTSSM_L123_SEND_EIDLE = 0x13,

	MSM_PCIE_LTSSM_L1_IDLE = 0x14,

	MSM_PCIE_LTSSM_L2_IDLE = 0x15,

	MSM_PCIE_LTSSM_L2_WAKE = 0x16,

	MSM_PCIE_LTSSM_DISABLED_ENTRY = 0x17,

	MSM_PCIE_LTSSM_DISABLED_IDLE = 0x18,

	MSM_PCIE_LTSSM_DISABLED = 0x19,

	MSM_PCIE_LTSSM_LPBK_ENTRY = 0x1a,

	MSM_PCIE_LTSSM_LPBK_ACTIVE = 0x1b,

	MSM_PCIE_LTSSM_LPBK_EXIT = 0x1c,

	MSM_PCIE_LTSSM_LPBK_EXIT_TIMEOUT = 0x1d,

	MSM_PCIE_LTSSM_HOT_RESET_ENTRY = 0x1e,

	MSM_PCIE_LTSSM_HOT_RESET = 0x1f,

};



static const char * const msm_pcie_ltssm_str[] = {

	[MSM_PCIE_LTSSM_DETECT_QUIET] = "LTSSM_DETECT_QUIET",

	[MSM_PCIE_LTSSM_DETECT_ACT] = "LTSSM_DETECT_ACT",

	[MSM_PCIE_LTSSM_POLL_ACTIVE] = "LTSSM_POLL_ACTIVE",

	[MSM_PCIE_LTSSM_POLL_COMPLIANCE] = "LTSSM_POLL_COMPLIANCE",

	[MSM_PCIE_LTSSM_POLL_CONFIG] = "LTSSM_POLL_CONFIG",

	[MSM_PCIE_LTSSM_PRE_DETECT_QUIET] = "LTSSM_PRE_DETECT_QUIET",

	[MSM_PCIE_LTSSM_DETECT_WAIT] = "LTSSM_DETECT_WAIT",

	[MSM_PCIE_LTSSM_CFG_LINKWD_START] = "LTSSM_CFG_LINKWD_START",

	[MSM_PCIE_LTSSM_CFG_LINKWD_ACEPT] = "LTSSM_CFG_LINKWD_ACEPT",

	[MSM_PCIE_LTSSM_CFG_LANENUM_WAIT] = "LTSSM_CFG_LANENUM_WAIT",

	[MSM_PCIE_LTSSM_CFG_LANENUM_ACEPT] = "LTSSM_CFG_LANENUM_ACEPT",

	[MSM_PCIE_LTSSM_CFG_COMPLETE] = "LTSSM_CFG_COMPLETE",

	[MSM_PCIE_LTSSM_CFG_IDLE] = "LTSSM_CFG_IDLE",

	[MSM_PCIE_LTSSM_RCVRY_LOCK] = "LTSSM_RCVRY_LOCK",

	[MSM_PCIE_LTSSM_RCVRY_SPEED] = "LTSSM_RCVRY_SPEED",

	[MSM_PCIE_LTSSM_RCVRY_RCVRCFG] = "LTSSM_RCVRY_RCVRCFG",

	[MSM_PCIE_LTSSM_RCVRY_IDLE] = "LTSSM_RCVRY_IDLE",

	[MSM_PCIE_LTSSM_RCVRY_EQ0] = "LTSSM_RCVRY_EQ0",

	[MSM_PCIE_LTSSM_RCVRY_EQ1] = "LTSSM_RCVRY_EQ1",

	[MSM_PCIE_LTSSM_RCVRY_EQ2] = "LTSSM_RCVRY_EQ2",

	[MSM_PCIE_LTSSM_RCVRY_EQ3] = "LTSSM_RCVRY_EQ3",

	[MSM_PCIE_LTSSM_L0] = "LTSSM_L0",

	[MSM_PCIE_LTSSM_L0S] = "LTSSM_L0S",

	[MSM_PCIE_LTSSM_L123_SEND_EIDLE] = "LTSSM_L123_SEND_EIDLE",

	[MSM_PCIE_LTSSM_L1_IDLE] = "LTSSM_L1_IDLE",

	[MSM_PCIE_LTSSM_L2_IDLE] = "LTSSM_L2_IDLE",

	[MSM_PCIE_LTSSM_L2_WAKE] = "LTSSM_L2_WAKE",

	[MSM_PCIE_LTSSM_DISABLED_ENTRY] = "LTSSM_DISABLED_ENTRY",

	[MSM_PCIE_LTSSM_DISABLED_IDLE] = "LTSSM_DISABLED_IDLE",

	[MSM_PCIE_LTSSM_DISABLED] = "LTSSM_DISABLED",

	[MSM_PCIE_LTSSM_LPBK_ENTRY] = "LTSSM_LPBK_ENTRY",

	[MSM_PCIE_LTSSM_LPBK_ACTIVE] = "LTSSM_LPBK_ACTIVE",

	[MSM_PCIE_LTSSM_LPBK_EXIT] = "LTSSM_LPBK_EXIT",

	[MSM_PCIE_LTSSM_LPBK_EXIT_TIMEOUT] = "LTSSM_LPBK_EXIT_TIMEOUT",

	[MSM_PCIE_LTSSM_HOT_RESET_ENTRY] = "LTSSM_HOT_RESET_ENTRY",

	[MSM_PCIE_LTSSM_HOT_RESET] = "LTSSM_HOT_RESET",

};



#define TO_LTSSM_STR(state) ((state) >= ARRAY_SIZE(msm_pcie_ltssm_str) ? \

				"LTSSM_INVALID" : msm_pcie_ltssm_str[state])



enum msm_pcie_debugfs_option {

	MSM_PCIE_OUTPUT_PCIE_INFO,

	MSM_PCIE_DISABLE_LINK,
@@ -3852,8 +3935,8 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev) 
	do {

		usleep_range(LINK_UP_TIMEOUT_US_MIN, LINK_UP_TIMEOUT_US_MAX);

		val =  readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS);

		PCIE_DBG(dev, "PCIe RC%d: LTSSM_STATE:0x%x\n",

			dev->rc_idx, (val >> 12) & 0x3f);

		PCIE_DBG(dev, "PCIe RC%d: LTSSM_STATE: %s\n",

			dev->rc_idx, TO_LTSSM_STR((val >> 12) & 0x3f));

	} while ((!(val & XMLH_LINK_UP) ||

		!msm_pcie_confirm_linkup(dev, false, false, NULL))

		&& (link_check_count++ < dev->link_check_max_count));