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Commit 8b7834cf authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: move to controller based memlat on kona"

parents c9c608fb ceb29d1a

bindings/devfreq/arm-memlat-mon.txt

+51 −28
Original line number Diff line number Diff line
@@ -3,21 +3,40 @@ ARM CPU memory latency monitor device 
arm-memlat-mon is a device that represents the use of the PMU in ARM cores

to measure the parameters for latency driven memory access patterns.



Required structure:

An instance of arm-memlat-mon must be described in two levels of device nodes.

The first level describes the controller while the second level describes the

monitors that the controller manages. At least one monitor is required per

controller.



[First Level Nodes]

Required properties:

- compatible:			Must be "qcom,arm-memlat-mon" or "qcom,arm-cpu-mon"

- qcom,cpulist:			List of CPU phandles to be monitored in a cluster

- qcom,target-dev:		The DT device that corresponds to this master port

- qcom,core-dev-table:		A mapping table of core frequency to a required bandwidth vote at the

				given core frequency.

- compatible:			Must be "qcom,arm-memlat-cpugrp"

- qcom,cpulist:			List of CPU phandles to be monitored in a

				cluster. Must be a superset of cpulists

				described in second level nodes.



[Second Level Nodes]

Required properties:

- compatible:			Must be "qcom,arm-memlat-mon" or

				"qcom,arm-compute-mon"

- qcom,target-dev:		The DT device that corresponds to this master

				port

- qcom,core-dev-table:		A mapping table of core frequency to a required

				bandwidth vote at the given core frequency.

- qcom,cachemiss-ev:		The cache miss event that this monitor is

				supposed to measure. Optional for compute only.

Optional properties:

- qcom,cachemiss-ev:		The cache miss event that this monitor is supposed to measure.

				Defaults to 0x17 if not specified.

- qcom,inst-ev:			The instruction count event that this monitor is supposed to measure.

				Defaults to 0x08 if not specified.

- qcom,stall-cycle-ev:		The stall cycle count that this monitor is supposed to measure.

				Assumes 100% stall if not specified.



- qcom,cpulist:			List of CPU phandles to be monitored in a

				cluster. Must be a subset of the cpulist

				described in first level node. Defaults to

				cpulist in first level node if not specified.

- qcom,inst-ev:			The instruction count event that this monitor is

				supposed to measure. Defaults to 0x08 if not

				specified.

- qcom,stall-cycle-ev:		The stall cycle count that this monitor is

				supposed to measure. Assumes 100% stall if not

				specified.

- qcom,ddr-type:		Optional property indicates ddr type which can support

				different frequencies for a given target.
@@ -26,9 +45,12 @@ Example: 
#define DDR_TYPE_LPDDR3	5

#define DDR_TYPE_LPDDR4X	7



	qcom,arm-memlat-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0 &CPU1>;



		qcom,arm-memlat-mon {

			compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1>;

			qcom,target-dev = <&memlat0>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,inst-ev = <0x08>;
@@ -48,3 +70,4 @@ Example: 
					< 1881600 5859 >;

			};

		};

	};

qcom/kona.dtsi

+158 −151
Original line number Diff line number Diff line
@@ -1140,9 +1140,57 @@ 
		qcom,count-unit = <0x10000>;

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;



		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_l3>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table =
@@ -1160,6 +1208,49 @@ 
				< 1670400 1382400000 >;

		};



		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,target-dev = <&cpu0_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS( 150, 16) >,

				<  729600 MHZ_TO_MBPS( 300, 16) >,

				< 1497600 MHZ_TO_MBPS( 466, 16) >,

				< 1670400 MHZ_TO_MBPS( 600, 16) >;

		};



		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x2A>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					<  300000 MHZ_TO_MBPS(  200, 4) >,

					<  729600 MHZ_TO_MBPS(  451, 4) >,

					< 1132800 MHZ_TO_MBPS(  547, 4) >,

					< 1497600 MHZ_TO_MBPS(  768, 4) >,

					< 1670400 MHZ_TO_MBPS( 1017, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					<  300000 MHZ_TO_MBPS(  200, 4) >,

					<  729600 MHZ_TO_MBPS(  451, 4) >,

					< 1132800 MHZ_TO_MBPS(  547, 4) >,

					< 1497600 MHZ_TO_MBPS(  768, 4) >,

					< 1670400 MHZ_TO_MBPS( 1017, 4) >;

			};

		};



	};



	cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;



		cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
@@ -1190,39 +1281,8 @@ 
				< 2227200 1382400000 >;

		};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&cpu0_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			<  300000 MHZ_TO_MBPS( 150, 16) >,

			<  729600 MHZ_TO_MBPS( 300, 16) >,

			< 1497600 MHZ_TO_MBPS( 466, 16) >,

			< 1670400 MHZ_TO_MBPS( 600, 16) >;

	};



	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



		cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			qcom,target-dev = <&cpu4_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =
@@ -1235,50 +1295,6 @@ 
				< 2476800 MHZ_TO_MBPS( 1000, 16) >;

		};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&cpu0_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x2A>;

		ddr4-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS(  200, 4) >,

				<  729600 MHZ_TO_MBPS(  451, 4) >,

				< 1132800 MHZ_TO_MBPS(  547, 4) >,

				< 1497600 MHZ_TO_MBPS(  768, 4) >,

				< 1670400 MHZ_TO_MBPS( 1017, 4) >;

		};



		ddr5-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR5>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS(  200, 4) >,

				<  729600 MHZ_TO_MBPS(  451, 4) >,

				< 1132800 MHZ_TO_MBPS(  547, 4) >,

				< 1497600 MHZ_TO_MBPS(  768, 4) >,

				< 1670400 MHZ_TO_MBPS( 1017, 4) >;

		};

	};



	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
@@ -1313,18 +1329,8 @@ 
			};

		};



	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu4_computemon: qcom,cpu4-computemon {

		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			compatible = "qcom,arm-compute-mon";

			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
@@ -1342,6 +1348,7 @@ 
					< 2500000 MHZ_TO_MBPS(2736, 4) >;

			};

		};

	};



	keepalive_opp_table: keepalive-opp-table {

		compatible = "operating-points-v2";