Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ceb29d1a authored by Amir Vajid's avatar Amir Vajid
Browse files

ARM: dts: msm: move to controller based memlat on kona 

Update kona to use the new controller based memlat design.

Change-Id: Ibaba50b42f61e739ecd9ce13ab0e66d1bb60559c
parent 511e2b6c

qcom/kona.dtsi

+158 −151
Original line number Diff line number Diff line
@@ -1140,9 +1140,57 @@ 
		qcom,count-unit = <0x10000>;

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;



		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_l3>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table =
@@ -1160,6 +1208,49 @@ 
				< 1670400 1382400000 >;

		};



		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,target-dev = <&cpu0_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS( 150, 16) >,

				<  729600 MHZ_TO_MBPS( 300, 16) >,

				< 1497600 MHZ_TO_MBPS( 466, 16) >,

				< 1670400 MHZ_TO_MBPS( 600, 16) >;

		};



		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x2A>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					<  300000 MHZ_TO_MBPS(  200, 4) >,

					<  729600 MHZ_TO_MBPS(  451, 4) >,

					< 1132800 MHZ_TO_MBPS(  547, 4) >,

					< 1497600 MHZ_TO_MBPS(  768, 4) >,

					< 1670400 MHZ_TO_MBPS( 1017, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					<  300000 MHZ_TO_MBPS(  200, 4) >,

					<  729600 MHZ_TO_MBPS(  451, 4) >,

					< 1132800 MHZ_TO_MBPS(  547, 4) >,

					< 1497600 MHZ_TO_MBPS(  768, 4) >,

					< 1670400 MHZ_TO_MBPS( 1017, 4) >;

			};

		};



	};



	cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;



		cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
@@ -1190,39 +1281,8 @@ 
				< 2227200 1382400000 >;

		};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&cpu0_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			<  300000 MHZ_TO_MBPS( 150, 16) >,

			<  729600 MHZ_TO_MBPS( 300, 16) >,

			< 1497600 MHZ_TO_MBPS( 466, 16) >,

			< 1670400 MHZ_TO_MBPS( 600, 16) >;

	};



	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



		cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			qcom,target-dev = <&cpu4_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =
@@ -1235,50 +1295,6 @@ 
				< 2476800 MHZ_TO_MBPS( 1000, 16) >;

		};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&cpu0_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x2A>;

		ddr4-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS(  200, 4) >,

				<  729600 MHZ_TO_MBPS(  451, 4) >,

				< 1132800 MHZ_TO_MBPS(  547, 4) >,

				< 1497600 MHZ_TO_MBPS(  768, 4) >,

				< 1670400 MHZ_TO_MBPS( 1017, 4) >;

		};



		ddr5-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR5>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS(  200, 4) >,

				<  729600 MHZ_TO_MBPS(  451, 4) >,

				< 1132800 MHZ_TO_MBPS(  547, 4) >,

				< 1497600 MHZ_TO_MBPS(  768, 4) >,

				< 1670400 MHZ_TO_MBPS( 1017, 4) >;

		};

	};



	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
@@ -1313,18 +1329,8 @@ 
			};

		};



	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu4_computemon: qcom,cpu4-computemon {

		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			compatible = "qcom,arm-compute-mon";

			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
@@ -1342,6 +1348,7 @@ 
					< 2500000 MHZ_TO_MBPS(2736, 4) >;

			};

		};

	};



	keepalive_opp_table: keepalive-opp-table {

		compatible = "operating-points-v2";