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Commit c9c608fb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: qcom: Add LPDDR4x and LPDDR5 freq tables on kona"

parents a340e048 d04ad5cd

bindings/devfreq/arm-memlat-mon.txt

+20 −5
Original line number Diff line number Diff line
@@ -18,9 +18,14 @@ Optional properties: 
- qcom,stall-cycle-ev:		The stall cycle count that this monitor is supposed to measure.

				Assumes 100% stall if not specified.





- qcom,ddr-type:		Optional property indicates ddr type which can support

				different frequencies for a given target.



Example:



#define DDR_TYPE_LPDDR3	5

#define DDR_TYPE_LPDDR4X	7



	qcom,arm-memlat-mon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1>;
@@ -28,8 +33,18 @@ Example: 
		qcom,cachemiss-ev = <0x2A>;

		qcom,inst-ev = <0x08>;

		qcom,stall-cycle-ev = <0xE7>;

		ddr3-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR3>;

			qcom,core-dev-table =

			<  300000 1525 >,

			<  499200 3143 >,

			< 1881600 5859 >;

		};

		ddr4-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

			qcom,core-dev-table =

				<  300000 1525 >,

				<  499200 3143 >,

				< 1881600 5859 >;

		};

	};

bindings/devfreq/devbw.txt

+20 −3
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ device is typically used to vote for BW requirements from a device's (Eg: 
CPU, GPU) master port(s) to the slave (Eg: DDR) port(s).



Required properties:

- compatible:		Must be "qcom,devbw"

- compatible:		Must be "qcom,devbw" or "qcom,devbw-ddr" or "qcom,devbw-llcc"

- qcom,src-dst-ports:	A list of tuples where each tuple consists of a bus

			master port number and a bus slave port number.

- operating-points-v2:	A phandle to the OPP v2 table that holds meaningful
@@ -14,44 +14,61 @@ Required properties: 
			requested from the device master port to the slave port.

			The list of values depend on the supported bus/slave

			frequencies and the bus width.



Optional properties:

- qcom,active-only:	Indicates that the bandwidth votes need to be

			enforced only when the CPU subsystem is active.

- governor:		Initial governor to use for the device.

			Default: "performance"



- opp-supported-hw:	For the devices that are compatible with "qcom, devbw-ddr",

			the OPP node can have opp-supported-hw property. This is a

			single 32 bit bitmap value, representing compatible DDR-Type in HW.

Example:

		    Value:

			0x80:	Frequency Compatible for LPDDR4X only

			0x100:	Frequency Compatible for LPDDR5 only

			0x180:	Frequency Compatible for both LPDDR4X and LPDDR5





Example:



	bw_opp_table: bw-opp-table {

		compatible = "operating-points-v2";

		opp-75  {

			opp-hz = /bits/ 64 <  572 >; /*  75 MHz */

			opp-supported-hw = <0x80>;

		};

		opp-150 {

			opp-hz = /bits/ 64 < 1144 >; /* 150 MHz */

			opp-supported-hw = <0x80>;

		};

		opp-200 {

			opp-hz = /bits/ 64 < 1525 >; /* 200 MHz */

			opp-supported-hw = <0x180>;

		};

		opp-307 {

			opp-hz = /bits/ 64 < 2342 >; /* 307 MHz */

			opp-supported-hw = <0x80>;

		};

		opp-460 {

			opp-hz = /bits/ 64 < 3509 >; /* 460 MHz */

			opp-supported-hw = <0x80>;

		};

		opp-614 {

			opp-hz = /bits/ 64 < 4684 >; /* 614 MHz */

			opp-supported-hw = <0x80>;

		};

		opp-800 {

			opp-hz = /bits/ 64 < 6103 >; /* 800 MHz */

			opp-supported-hw = <0x80>;

		};

		opp-931 {

			opp-hz = /bits/ 64 < 7102 >; /* 931 MHz */

			opp-supported-hw = <0x80>;

		};

	};

	qcom,cpubw {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw-ddr";

		qcom,src-dst-ports = <1 512>, <2 512>;

		qcom,active-only;

		operating-points-v2 = <&bw_opp_table>;

qcom/kona.dtsi

+119 −56
Original line number Diff line number Diff line
@@ -19,6 +19,12 @@ 
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}



#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\

				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\

				opp-supported-hw = <ddrtype>;}



#define DDR_TYPE_LPDDR4X	7

#define DDR_TYPE_LPDDR5		8



/ {

	model = "Qualcomm Technologies, Inc. kona";
@@ -997,35 +1003,35 @@ 


	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(  200, 4); /*   762 MB/s */

		BW_OPP_ENTRY(  300, 4); /*  1144 MB/s */

		BW_OPP_ENTRY(  451, 4); /*  1720 MB/s */

		BW_OPP_ENTRY(  547, 4); /*  2086 MB/s */

		BW_OPP_ENTRY(  681, 4); /*  2597 MB/s */

		BW_OPP_ENTRY(  768, 4); /*  2929 MB/s */

		BW_OPP_ENTRY( 1017, 4); /*  3879 MB/s */

		BW_OPP_ENTRY( 1353, 4); /*  5161 MB/s */

		BW_OPP_ENTRY( 1555, 4); /*  5931 MB/s */

		BW_OPP_ENTRY( 1804, 4); /*  6881 MB/s */

		BW_OPP_ENTRY( 2092, 4); /*  7980 MB/s */

		BW_OPP_ENTRY( 2736, 4); /* 10437 MB/s */

		BW_OPP_ENTRY_DDR(  200, 4, 0x180); /*   762 MB/s */

		BW_OPP_ENTRY_DDR(  300, 4, 0x180); /*  1144 MB/s */

		BW_OPP_ENTRY_DDR(  451, 4, 0x180); /*  1720 MB/s */

		BW_OPP_ENTRY_DDR(  547, 4, 0x180); /*  2086 MB/s */

		BW_OPP_ENTRY_DDR(  681, 4, 0x180); /*  2597 MB/s */

		BW_OPP_ENTRY_DDR(  768, 4, 0x180); /*  2929 MB/s */

		BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /*  3879 MB/s */

		BW_OPP_ENTRY_DDR( 1353, 4,  0x80); /*  5161 MB/s */

		BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /*  5931 MB/s */

		BW_OPP_ENTRY_DDR( 1804, 4, 0x180); /*  6881 MB/s */

		BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /*  7980 MB/s */

		BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */

	};



	suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(    0, 4); /*     0 MB/s */

		BW_OPP_ENTRY(  200, 4); /*   762 MB/s */

		BW_OPP_ENTRY(  300, 4); /*  1144 MB/s */

		BW_OPP_ENTRY(  451, 4); /*  1720 MB/s */

		BW_OPP_ENTRY(  547, 4); /*  2086 MB/s */

		BW_OPP_ENTRY(  681, 4); /*  2597 MB/s */

		BW_OPP_ENTRY(  768, 4); /*  2929 MB/s */

		BW_OPP_ENTRY( 1017, 4); /*  3879 MB/s */

		BW_OPP_ENTRY( 1353, 4); /*  5161 MB/s */

		BW_OPP_ENTRY( 1555, 4); /*  5931 MB/s */

		BW_OPP_ENTRY( 1804, 4); /*  6881 MB/s */

		BW_OPP_ENTRY( 2092, 4); /*  7980 MB/s */

		BW_OPP_ENTRY( 2736, 4); /* 10437 MB/s */

		BW_OPP_ENTRY_DDR(    0, 4, 0x180); /*     0 MB/s */

		BW_OPP_ENTRY_DDR(  200, 4, 0x180); /*   762 MB/s */

		BW_OPP_ENTRY_DDR(  300, 4, 0x180); /*  1144 MB/s */

		BW_OPP_ENTRY_DDR(  451, 4, 0x180); /*  1720 MB/s */

		BW_OPP_ENTRY_DDR(  547, 4, 0x180); /*  2086 MB/s */

		BW_OPP_ENTRY_DDR(  681, 4, 0x180); /*  2597 MB/s */

		BW_OPP_ENTRY_DDR(  768, 4, 0x180); /*  2929 MB/s */

		BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /*  3879 MB/s */

		BW_OPP_ENTRY_DDR( 1353, 4,  0x80); /*  5161 MB/s */

		BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /*  5931 MB/s */

		BW_OPP_ENTRY_DDR( 1804, 4, 0x180); /*  6881 MB/s */

		BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /*  7980 MB/s */

		BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */

	};



	llcc_pmu: llcc-pmu@9095000 {
@@ -1055,7 +1061,7 @@ 
	};



	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
@@ -1073,14 +1079,14 @@ 
		qcom,count-unit = <0x10000>;

	};



	npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {

	npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;

		operating-points-v2 = <&suspendable_llcc_bw_opp_table>;

	};



	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@60300 {

	npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@60300 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00060400 0x300>, <0x00060300 0x200>;

		reg-names = "base", "global_base";
@@ -1091,12 +1097,29 @@ 
		interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_npu_ddr_bw>;

		qcom,target-dev = <&npu_npu_llcc_bw>;

		qcom,count-unit = <0x10000>;

	};



	npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

	};



	npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@0x9092000 {

		compatible = "qcom,bimc-bwmon5";

		reg = <0x9092000 0x1000>;

		reg-names = "base";

		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_llcc_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};



	npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
@@ -1213,7 +1236,7 @@ 
	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
@@ -1226,6 +1249,8 @@ 
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&cpu0_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x2A>;

		ddr4-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS(  200, 4) >,

				<  729600 MHZ_TO_MBPS(  451, 4) >,
@@ -1234,8 +1259,19 @@ 
				< 1670400 MHZ_TO_MBPS( 1017, 4) >;

		};



		ddr5-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR5>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS(  200, 4) >,

				<  729600 MHZ_TO_MBPS(  451, 4) >,

				< 1132800 MHZ_TO_MBPS(  547, 4) >,

				< 1497600 MHZ_TO_MBPS(  768, 4) >,

				< 1670400 MHZ_TO_MBPS( 1017, 4) >;

		};

	};



	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
@@ -1248,6 +1284,8 @@ 
		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		qcom,target-dev = <&cpu4_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x2A>;

		ddr4-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS( 200, 4) >,

				<  691200 MHZ_TO_MBPS( 451, 4) >,
@@ -1257,12 +1295,26 @@ 
				< 1574400 MHZ_TO_MBPS(1353, 4) >,

				< 1804800 MHZ_TO_MBPS(1555, 4) >,

				< 2227200 MHZ_TO_MBPS(1804, 4) >,

				< 2380800 MHZ_TO_MBPS(2092, 4) >;

		};



		ddr5-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR5>;

			qcom,core-dev-table =

				<  300000 MHZ_TO_MBPS( 200, 4) >,

				<  691200 MHZ_TO_MBPS( 451, 4) >,

				<  806400 MHZ_TO_MBPS( 547, 4) >,

				< 1017600 MHZ_TO_MBPS( 768, 4) >,

				< 1228800 MHZ_TO_MBPS(1017, 4) >,

				< 1804800 MHZ_TO_MBPS(1555, 4) >,

				< 2227200 MHZ_TO_MBPS(1804, 4) >,

				< 2380800 MHZ_TO_MBPS(2092, 4) >,

				< 2476800 MHZ_TO_MBPS(2736, 4) >;

		};

	};



	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw-ddr";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
@@ -1274,11 +1326,22 @@ 
		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;

		ddr4-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

			qcom,core-dev-table =

				< 1804800 MHZ_TO_MBPS( 200, 4) >,

				< 2380800 MHZ_TO_MBPS(1017, 4) >,

				< 2500000 MHZ_TO_MBPS(2092, 4) >;

		};



		ddr5-map {

			qcom,ddr-type = <DDR_TYPE_LPDDR5>;

			qcom,core-dev-table =

				< 1804800 MHZ_TO_MBPS( 200, 4) >,

				< 2380800 MHZ_TO_MBPS(1017, 4) >,

				< 2500000 MHZ_TO_MBPS(2736, 4) >;

		};

	};



	keepalive_opp_table: keepalive-opp-table {

		compatible = "operating-points-v2";