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Commit 71422dbb authored by Alex Frid's avatar Alex Frid Committed by Stephen Boyd
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clk: tegra: Correct Tegra210 UTMIPLL poweron delay



Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us).
Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT
and ENABLE_DLY_COUNT fields.

Signed-off-by: default avatarAlex Frid <afrid@nvidia.com>
Reviewed-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: default avatarJon Mayo <jmayo@nvidia.com>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 2f924ac3
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