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Commit 71422dbb authored by Alex Frid's avatar Alex Frid Committed by Stephen Boyd
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clk: tegra: Correct Tegra210 UTMIPLL poweron delay 



Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us).
Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT
and ENABLE_DLY_COUNT fields.

Signed-off-by: default avatarAlex Frid <afrid@nvidia.com>
Reviewed-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: default avatarJon Mayo <jmayo@nvidia.com>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 2f924ac3

drivers/clk/tegra/clk-tegra210.c

+3 −3
Original line number Diff line number Diff line
@@ -2472,15 +2472,14 @@ static void tegra210_utmi_param_configure(void) 
	reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);



	reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);



	reg |=

	UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);

	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);



	/* Program UTMIP PLL delay and oscillator frequency counts */

	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);

	reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);



	reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);

	reg |=

	UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
@@ -2496,7 +2495,8 @@ static void tegra210_utmi_param_configure(void) 
	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;

	reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;

	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);

	udelay(1);



	udelay(20);



	/* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */

	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);