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Commit 6895ae80 authored by Satya Rama Aditya Pinapala's avatar Satya Rama Aditya Pinapala Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: Update data lane control registers 



Update the DSI PHY programming as per the latest Hardware
recommendation.

Change-Id: I3b4bcf0e01645089d338e5b36d219e86e4527de7
Signed-off-by: default avatarSatya Rama Aditya Pinapala <psraditya30@codeaurora.org>
parent cf725323
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