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Commit 6895ae80 authored by Satya Rama Aditya Pinapala's avatar Satya Rama Aditya Pinapala Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: Update data lane control registers 



Update the DSI PHY programming as per the latest Hardware
recommendation.

Change-Id: I3b4bcf0e01645089d338e5b36d219e86e4527de7
Signed-off-by: default avatarSatya Rama Aditya Pinapala <psraditya30@codeaurora.org>
parent cf725323

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c

+8 −1
Original line number Diff line number Diff line
@@ -113,7 +113,14 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, 
			    struct dsi_phy_cfg *cfg)

{

	int i;

	u8 tx_dctrl[] = {0x00, 0x00, 0x00, 0x04, 0x01};

	u8 tx_dctrl_v4[] = {0x00, 0x00, 0x00, 0x04, 0x01};

	u8 tx_dctrl_v4_1[] = {0x40, 0x40, 0x40, 0x46, 0x41};

	u8 *tx_dctrl;



	if (phy->version == DSI_PHY_VERSION_4_1)

		tx_dctrl = &tx_dctrl_v4_1[0];

	else

		tx_dctrl = &tx_dctrl_v4[0];



	/* Strength ctrl settings */

	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {