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Commit 4a057dc7 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove qcom,gpu-offset 



Now that 4xx is gone 3xx is the only target that directly programs SMMU
registers during pagetable switch which means that we now have a fixed
target specific register offset. Use that and get rid of the iommu
functions to store and use the qcom,qpu_offset property from the device
tree.

Change-Id: Ic0dedbadead97c63bbdbb969adaae1c594e0eccd
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent e4518d2c

drivers/gpu/msm/adreno_iommu.c

+9 −16
Original line number Diff line number Diff line
@@ -92,37 +92,30 @@ static unsigned int _vbif_unlock(struct adreno_device *adreno_dev, 
	return cmds - start;

}



#define A3XX_GPU_OFFSET 0xa000



/* This function is only needed for A3xx targets */

static unsigned int _cp_smmu_reg(struct adreno_device *adreno_dev,

				unsigned int *cmds,

				enum kgsl_iommu_reg_map reg,

				unsigned int num)

{

	unsigned int *start = cmds;

	unsigned int offset;



	offset = kgsl_mmu_get_reg_ahbaddr(KGSL_MMU(adreno_dev),

					  KGSL_IOMMU_CONTEXT_USER, reg) >> 2;

	unsigned int offset = (A3XX_GPU_OFFSET + kgsl_iommu_reg_list[reg]) >> 2;



	/* Required for a3x, a4x, a5x families */

	if (adreno_is_a5xx(adreno_dev)) {

		*cmds++ = cp_register(adreno_dev, offset, num);

	} else if (adreno_is_a3xx(adreno_dev)) {

	*cmds++ = cp_packet(adreno_dev, CP_REG_WR_NO_CTXT, num + 1);

	*cmds++ = offset;

	}



	return cmds - start;

}



/* This function is only needed for A3xx targets */

static unsigned int _tlbiall(struct adreno_device *adreno_dev,

				unsigned int *cmds)

{

	unsigned int *start = cmds;

	unsigned int tlbstatus;



	tlbstatus = kgsl_mmu_get_reg_ahbaddr(KGSL_MMU(adreno_dev),

			KGSL_IOMMU_CONTEXT_USER,

			KGSL_IOMMU_CTX_TLBSTATUS) >> 2;

	unsigned int tlbstatus = (A3XX_GPU_OFFSET +

		kgsl_iommu_reg_list[KGSL_IOMMU_CTX_TLBSTATUS]) >> 2;



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TLBIALL, 1);

	*cmds++ = 1;

drivers/gpu/msm/kgsl_iommu.c

+0 −29
Original line number Diff line number Diff line
@@ -1446,23 +1446,6 @@ static struct kgsl_pagetable *kgsl_iommu_getpagetable(struct kgsl_mmu *mmu, 
	return pt;

}



/*

 * kgsl_iommu_get_reg_ahbaddr - Returns the ahb address of the register

 * @mmu - Pointer to mmu structure

 * @id - The context ID of the IOMMU ctx

 * @reg - The register for which address is required

 *

 * Return - The address of register which can be used in type0 packet

 */

static unsigned int kgsl_iommu_get_reg_ahbaddr(struct kgsl_mmu *mmu,

		int id, unsigned int reg)

{

	struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu);

	struct kgsl_iommu_context *ctx = &iommu->ctx[id];



	return ctx->gpu_offset + kgsl_iommu_reg_list[reg];

}



static void _detach_context(struct kgsl_iommu_context *ctx)

{

	struct kgsl_iommu_pt *iommu_pt;
@@ -1550,13 +1533,6 @@ static int kgsl_iommu_init(struct kgsl_mmu *mmu) 
	if (status)

		return status;



	/* check requirements for per process pagetables */

	if (ctx->gpu_offset == UINT_MAX) {

		dev_err(device->dev,

			"missing qcom,gpu-offset forces global pt\n");

		mmu->features |= KGSL_MMU_GLOBAL_PAGETABLE;

	}



	/* Check to see if we need to do the IOMMU sync dance */

	need_iommu_sync = of_property_read_bool(device->pdev->dev.of_node,

		"qcom,gpu-quirk-iommu-sync");
@@ -2621,10 +2597,6 @@ static int _kgsl_iommu_cb_probe(struct kgsl_device *device, 
	if (ctx->id == KGSL_IOMMU_CONTEXT_SECURE)

		device->mmu.secured = true;



	/* this property won't be found for all context banks */

	if (of_property_read_u32(node, "qcom,gpu-offset", &ctx->gpu_offset))

		ctx->gpu_offset = UINT_MAX;



	ctx->kgsldev = device;



	/* arm-smmu driver we'll have the right device pointer here. */
@@ -2758,7 +2730,6 @@ struct kgsl_mmu_ops kgsl_iommu_ops = { 
	.mmu_get_current_ttbr0 = kgsl_iommu_get_current_ttbr0,

	.mmu_enable_clk = kgsl_iommu_enable_clk,

	.mmu_disable_clk = kgsl_iommu_disable_clk,

	.mmu_get_reg_ahbaddr = kgsl_iommu_get_reg_ahbaddr,

	.mmu_pt_equal = kgsl_iommu_pt_equal,

	.mmu_set_pf_policy = kgsl_iommu_set_pf_policy,

	.mmu_pagefault_resume = kgsl_iommu_pagefault_resume,

drivers/gpu/msm/kgsl_iommu.h

+0 −2
Original line number Diff line number Diff line
@@ -86,7 +86,6 @@ enum kgsl_iommu_context_id { 
 * @kgsldev: The kgsl device that uses this context.

 * @fault: Flag when set indicates that this iommu device has caused a page

 * fault

 * @gpu_offset: Offset of this context bank in the GPU register space

 * @default_pt: The default pagetable for this context,

 *		it may be changed by self programming.

 */
@@ -98,7 +97,6 @@ struct kgsl_iommu_context { 
	struct kgsl_device *kgsldev;

	int fault;

	void __iomem *regbase;

	unsigned int gpu_offset;

	struct kgsl_pagetable *default_pt;

};

drivers/gpu/msm/kgsl_mmu.h

+0 −20
Original line number Diff line number Diff line
@@ -61,8 +61,6 @@ struct kgsl_mmu_ops { 
	void (*mmu_clear_fsr)(struct kgsl_mmu *mmu);

	void (*mmu_enable_clk)(struct kgsl_mmu *mmu);

	void (*mmu_disable_clk)(struct kgsl_mmu *mmu);

	unsigned int (*mmu_get_reg_ahbaddr)(struct kgsl_mmu *mmu,

			int ctx_id, unsigned int reg);

	bool (*mmu_pt_equal)(struct kgsl_mmu *mmu,

			struct kgsl_pagetable *pt, u64 ttbr0);

	int (*mmu_set_pf_policy)(struct kgsl_mmu *mmu, unsigned long pf_policy);
@@ -309,24 +307,6 @@ static inline void kgsl_mmu_disable_clk(struct kgsl_mmu *mmu) 
		mmu->mmu_ops->mmu_disable_clk(mmu);

}



/*

 * kgsl_mmu_get_reg_ahbaddr() - Calls the mmu specific function pointer to

 * return the address that GPU can use to access register

 * @mmu:		Pointer to the device mmu

 * @ctx_id:		The MMU HW context ID

 * @reg:		Register whose address is to be returned

 *

 * Returns the ahb address of reg else 0

 */

static inline unsigned int kgsl_mmu_get_reg_ahbaddr(struct kgsl_mmu *mmu,

				int ctx_id, unsigned int reg)

{

	if (MMU_OP_VALID(mmu, mmu_get_reg_ahbaddr))

		return mmu->mmu_ops->mmu_get_reg_ahbaddr(mmu, ctx_id, reg);



	return 0;

}



static inline int kgsl_mmu_set_pagefault_policy(struct kgsl_mmu *mmu,

						unsigned long pf_policy)

{