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Commit e4518d2c authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Drop SMMUv1 support 



We haven't had any targets that use SMMUv1 for quite a while and it
isn't likely that we will ever release a target that will need it
again.

Change-Id: Ic0dedbad8e04e27bb9c5a4c833736a2106c36025
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 1fe7f363

drivers/gpu/msm/adreno_iommu.c

+11 −227
Original line number Diff line number Diff line
@@ -46,74 +46,6 @@ static unsigned int _wait_reg(struct adreno_device *adreno_dev, 
#define KGSL_MMU(_dev) \

	((struct kgsl_mmu *) (&(KGSL_DEVICE((_dev))->mmu)))



static unsigned int  _iommu_lock(struct adreno_device *adreno_dev,

				 unsigned int *cmds)

{

	unsigned int *start = cmds;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);



	/*

	 * If we don't have this register, probe should have forced

	 * global pagetables and we shouldn't get here.

	 */

	if (WARN_ONCE(iommu->micro_mmu_ctrl == UINT_MAX,

		"invalid GPU IOMMU lock sequence\n"))

		return 0;



	/*

	 * glue commands together until next

	 * WAIT_FOR_ME

	 */

	cmds += _wait_reg(adreno_dev, cmds,

			adreno_getreg(adreno_dev, ADRENO_REG_CP_WFI_PEND_CTR),

			1, 0xFFFFFFFF, 0xF);



	/* set the iommu lock bit */

	*cmds++ = cp_packet(adreno_dev, CP_REG_RMW, 3);

	*cmds++ = iommu->micro_mmu_ctrl >> 2;

	/* AND to unmask the lock bit */

	*cmds++ = ~(KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_HALT);

	/* OR to set the IOMMU lock bit */

	*cmds++ = KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_HALT;



	/* wait for smmu to lock */

	cmds += _wait_reg(adreno_dev, cmds, iommu->micro_mmu_ctrl >> 2,

			KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_IDLE,

			KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_IDLE, 0xF);



	return cmds - start;

}



static unsigned int _iommu_unlock(struct adreno_device *adreno_dev,

				  unsigned int *cmds)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);

	unsigned int *start = cmds;



	/*

	 * If we don't have this register, probe should have forced

	 * global pagetables and we shouldn't get here.

	 */

	if (WARN_ONCE(iommu->micro_mmu_ctrl == UINT_MAX,

		"invalid GPU IOMMU unlock sequence\n"))

		return 0;



	/* unlock the IOMMU lock */

	*cmds++ = cp_packet(adreno_dev, CP_REG_RMW, 3);

	*cmds++ = iommu->micro_mmu_ctrl >> 2;

	/* AND to unmask the lock bit */

	*cmds++ = ~(KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_HALT);

	/* OR with 0 so lock bit is unset */

	*cmds++ = 0;



	/* release all commands since _iommu_lock() with wait_for_me */

	cmds += cp_wait_for_me(adreno_dev, cmds);



	return cmds - start;

}



static unsigned int _vbif_lock(struct adreno_device *adreno_dev,

			unsigned int *cmds)

{
@@ -165,8 +97,6 @@ static unsigned int _cp_smmu_reg(struct adreno_device *adreno_dev, 
				enum kgsl_iommu_reg_map reg,

				unsigned int num)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);

	unsigned int *start = cmds;

	unsigned int offset;
@@ -174,7 +104,7 @@ static unsigned int _cp_smmu_reg(struct adreno_device *adreno_dev, 
					  KGSL_IOMMU_CONTEXT_USER, reg) >> 2;



	/* Required for a3x, a4x, a5x families */

	if (adreno_is_a5xx(adreno_dev) || iommu->version == 1) {

	if (adreno_is_a5xx(adreno_dev)) {

		*cmds++ = cp_register(adreno_dev, offset, num);

	} else if (adreno_is_a3xx(adreno_dev)) {

		*cmds++ = cp_packet(adreno_dev, CP_REG_WR_NO_CTXT, num + 1);
@@ -327,144 +257,6 @@ static inline int _adreno_iommu_add_idle_indirect_cmds( 
	return cmds - start;

}



/**

 * _adreno_mmu_set_pt_update_condition() - Generate commands to setup a

 * flag to indicate whether pt switch is required or not by comparing

 * current pt id and incoming pt id

 * @rb: The RB on which the commands will execute

 * @cmds: The pointer to memory where the commands are placed.

 * @ptname: Incoming pt id to set to

 *

 * Returns number of commands added.

 */

static unsigned int _adreno_mmu_set_pt_update_condition(

			struct adreno_ringbuffer *rb,

			unsigned int *cmds, unsigned int ptname)

{

	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);

	unsigned int *cmds_orig = cmds;

	/*

	 * write 1 to switch pt flag indicating that we need to execute the

	 * pt switch commands

	 */

	*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 1);

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(switch_pt_enable)));

	*cmds++ = 1;

	*cmds++ = cp_packet(adreno_dev, CP_WAIT_MEM_WRITES, 1);

	*cmds++ = 0;

	cmds += cp_wait_for_me(adreno_dev, cmds);

	/*

	 * The current ptname is

	 * directly compared to the incoming pt id

	 */

	*cmds++ = cp_mem_packet(adreno_dev, CP_COND_WRITE, 6, 2);

	/* write to mem space, when a mem space is equal to ref val */

	*cmds++ = (1 << 8) | (1 << 4) | 3;

	cmds += cp_gpuaddr(adreno_dev, cmds,

	   (adreno_dev->ringbuffers[0].pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(current_global_ptname)));

	*cmds++ = ptname;

	*cmds++ = 0xFFFFFFFF;

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(switch_pt_enable)));

	*cmds++ = 0;

	*cmds++ = cp_packet(adreno_dev, CP_WAIT_MEM_WRITES, 1);

	*cmds++ = 0;

	cmds += cp_wait_for_me(adreno_dev, cmds);



	return cmds - cmds_orig;

}



/**

 * _adreno_iommu_pt_update_pid_to_mem() - Add commands to write to memory the

 * pagetable id.

 * @rb: The ringbuffer on which these commands will execute

 * @cmds: Pointer to memory where the commands are copied

 * @ptname: The pagetable id

 */

static unsigned int _adreno_iommu_pt_update_pid_to_mem(

				struct adreno_ringbuffer *rb,

				unsigned int *cmds, int ptname)

{

	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);

	unsigned int *cmds_orig = cmds;



	*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 1);

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(current_rb_ptname)));

	*cmds++ = ptname;

	*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 1);

	cmds += cp_gpuaddr(adreno_dev, cmds,

		(adreno_dev->ringbuffers[0].pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(current_global_ptname)));

	*cmds++ = ptname;

	/* pagetable switch done, Housekeeping: set the switch_pt_enable to 0 */

	*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 1);

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(switch_pt_enable)));

	*cmds++ = 0;

	*cmds++ = cp_packet(adreno_dev, CP_WAIT_MEM_WRITES, 1);

	*cmds++ = 0;

	cmds += cp_wait_for_me(adreno_dev, cmds);



	return cmds - cmds_orig;

}



static unsigned int _adreno_iommu_set_pt_v1(struct adreno_ringbuffer *rb,

					unsigned int *cmds_orig,

					u64 ttbr0, u32 contextidr, u32 ptname)

{

	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);

	unsigned int *cmds = cmds_orig;

	unsigned int *cond_exec_ptr;



	cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);



	/* set flag that indicates whether pt switch is required*/

	cmds += _adreno_mmu_set_pt_update_condition(rb, cmds, ptname);

	*cmds++ = cp_mem_packet(adreno_dev, CP_COND_EXEC, 4, 2);

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(switch_pt_enable)));

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		PT_INFO_OFFSET(switch_pt_enable)));

	*cmds++ = 1;

	/* Exec count to be filled later */

	cond_exec_ptr = cmds;

	cmds++;



	cmds += cp_wait_for_idle(adreno_dev, cmds);



	cmds += _iommu_lock(adreno_dev, cmds);



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TTBR0, 2);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	cmds += _cp_smmu_reg(adreno_dev, cmds,

			KGSL_IOMMU_CTX_CONTEXTIDR, 1);

	*cmds++ = contextidr;



	/* a3xx doesn't have MEQ space to hold the TLBI commands */

	if (adreno_is_a3xx(adreno_dev))

		cmds += _iommu_unlock(adreno_dev, cmds);



	cmds += _tlbiall(adreno_dev, cmds);



	/* unlock or wait for me to finish the TLBI */

	if (!adreno_is_a3xx(adreno_dev))

		cmds += _iommu_unlock(adreno_dev, cmds);

	else

		cmds += cp_wait_for_me(adreno_dev, cmds);



	/* Exec count ordinal of CP_COND_EXEC packet */

	*cond_exec_ptr = (cmds - cond_exec_ptr - 1);

	cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);

	cmds += _adreno_iommu_pt_update_pid_to_mem(rb, cmds, ptname);



	return cmds - cmds_orig;

}





static unsigned int _adreno_iommu_set_pt_v2_a3xx(struct kgsl_device *device,

					unsigned int *cmds_orig,

					u64 ttbr0, u32 contextidr)
@@ -587,7 +379,6 @@ unsigned int adreno_iommu_set_pt_generate_cmds( 
	cmds += _adreno_iommu_add_idle_indirect_cmds(adreno_dev, cmds,

		iommu->setstate.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET);



	if (iommu->version >= 2) {

	if (adreno_is_a6xx(adreno_dev))

		cmds += _adreno_iommu_set_pt_v2_a6xx(device, cmds,

					ttbr0, contextidr, rb,
@@ -598,13 +389,6 @@ unsigned int adreno_iommu_set_pt_generate_cmds( 
	else if (adreno_is_a3xx(adreno_dev))

		cmds += _adreno_iommu_set_pt_v2_a3xx(device, cmds,

					ttbr0, contextidr);

		else

			WARN_ONCE(1,

			"GPU IOMMU set pagetable sequence not defined\n");

	} else {

		cmds += _adreno_iommu_set_pt_v1(rb, cmds, ttbr0, contextidr,

						pt->name);

	}



	/* invalidate all base pointers */

	cmds += cp_invalidate_state(adreno_dev, cmds);

drivers/gpu/msm/kgsl_iommu.c

+0 −16
Original line number Diff line number Diff line
@@ -1557,12 +1557,6 @@ static int kgsl_iommu_init(struct kgsl_mmu *mmu) 
		mmu->features |= KGSL_MMU_GLOBAL_PAGETABLE;

	}



	if (iommu->version == 1 && iommu->micro_mmu_ctrl == UINT_MAX) {

		dev_err(device->dev,

			"missing qcom,micro-mmu-control forces global pt\n");

		mmu->features |= KGSL_MMU_GLOBAL_PAGETABLE;

	}



	/* Check to see if we need to do the IOMMU sync dance */

	need_iommu_sync = of_property_read_bool(device->pdev->dev.of_node,

		"qcom,gpu-quirk-iommu-sync");
@@ -2670,11 +2664,6 @@ static int _kgsl_iommu_probe(struct kgsl_device *device, 


	memset(iommu, 0, sizeof(*iommu));



	if (of_device_is_compatible(node, "qcom,kgsl-smmu-v1"))

		iommu->version = 1;

	else

		iommu->version = 2;



	if (of_property_read_u32_array(node, "reg", reg_val, 2)) {

		dev_err(device->dev,

			"dt: Unable to read KGSL IOMMU register range\n");
@@ -2714,10 +2703,6 @@ static int _kgsl_iommu_probe(struct kgsl_device *device, 
			device->mmu.features |= kgsl_iommu_features[i].bit;

	}



	if (of_property_read_u32(node, "qcom,micro-mmu-control",

		&iommu->micro_mmu_ctrl))

		iommu->micro_mmu_ctrl = UINT_MAX;



	if (of_property_read_u32(node, "qcom,secure_align_mask",

		&device->mmu.secure_align_mask))

		device->mmu.secure_align_mask = 0xfff;
@@ -2743,7 +2728,6 @@ static const struct { 
	char *compat;

	int (*probe)(struct kgsl_device *device, struct device_node *node);

} kgsl_dt_devices[] = {

	{ "qcom,kgsl-smmu-v1", _kgsl_iommu_probe },

	{ "qcom,kgsl-smmu-v2", _kgsl_iommu_probe },

};

drivers/gpu/msm/kgsl_iommu.h

+0 −7
Original line number Diff line number Diff line
@@ -43,10 +43,6 @@ 
/* TLBSTATUS register fields */

#define KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE BIT(0)



/* IMPLDEF_MICRO_MMU_CTRL register fields */

#define KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_HALT  0x00000004

#define KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_IDLE  0x00000008



/* SCTLR fields */

#define KGSL_IOMMU_SCTLR_HUPCF_SHIFT		8

#define KGSL_IOMMU_SCTLR_CFCFG_SHIFT		7
@@ -115,7 +111,6 @@ struct kgsl_iommu_context { 
 * @setstate: Scratch GPU memory for IOMMU operations

 * @clk_enable_count: The ref count of clock enable calls

 * @clks: Array of pointers to IOMMU clocks

 * @micro_mmu_ctrl: GPU register offset of this glob al register

 * @smmu_info: smmu info used in a5xx preemption

 * @protect: register protection settings for the iommu.

 * @pagefault_suppression_count: Total number of pagefaults
@@ -129,9 +124,7 @@ struct kgsl_iommu { 
	struct kgsl_memdesc setstate;

	atomic_t clk_enable_count;

	struct clk *clks[KGSL_IOMMU_MAX_CLKS];

	unsigned int micro_mmu_ctrl;

	struct kgsl_memdesc smmu_info;

	unsigned int version;

	struct kgsl_protected_registers protect;

	u32 pagefault_suppression_count;

};