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Commit 3c753a6e authored by James Morse's avatar James Morse Committed by Srinivas Ramana
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arm64: Workaround Cortex-A77 erratum 1542418 on boot due to kexec 



Kexec allows us to inherit dirty ASIDs from a previous kernel. We can't
wait until the next ASID rollover to cleanup, do it early as part of
the cpu-errata's enable callback.

This extends __arm64_workaround_1542418_asid_rollover() to put everything
back as it was.

Change-Id: Ib560a10ec3c6c7d299f5874217c81ebe11cf0103
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
[suzuki.poulose@arm.com: skip CPUs not affected, refactor
cpu_enable callback ]
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Patch-mainline: linux-arm-kernel @ 11/14/19, 14:59
[sramana@codeaurora.org: Resolve trivial merge conflicts]
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent fe43b6c3

arch/arm64/include/asm/mmu_context.h

+1 −0
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, 


void verify_cpu_asid_bits(void);

void post_ttbr_update_workaround(void);

void arm64_workaround_1542418_asid_rollover(void);



#endif /* !__ASSEMBLY__ */

arch/arm64/kernel/cpu_errata.c

+14 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <asm/cpu.h>

#include <asm/cputype.h>

#include <asm/cpufeature.h>

#include <asm/mmu_context.h>

#include <asm/smp_plat.h>



static bool __maybe_unused
@@ -643,6 +644,18 @@ needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 
	return false;

}



#ifdef CONFIG_ARM64_ERRATUM_1542418

static void run_workaround_1542418_asid_rollover(const struct arm64_cpu_capabilities *c)

{

	/*

	 * If this CPU is affected by the erratum, run the workaround

	 * to protect us in case we are running on a kexec'ed kernel.

	 */

	if (c->matches(c, SCOPE_LOCAL_CPU))

		arm64_workaround_1542418_asid_rollover();

}

#endif



#ifdef CONFIG_HARDEN_EL2_VECTORS



static const struct midr_range arm64_harden_el2_vectors[] = {
@@ -881,6 +894,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.desc = "ARM erratum 1542418",

		.capability = ARM64_WORKAROUND_1542418,

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),

		.cpu_enable = run_workaround_1542418_asid_rollover,

	},

#endif

	{

arch/arm64/mm/context.c

+17 −0
Original line number Diff line number Diff line
@@ -140,6 +140,23 @@ static void __arm64_workaround_1542418_asid_rollover(void) 
	 */

}



void arm64_workaround_1542418_asid_rollover(void)

{

	u64 ttbr0 = read_sysreg(ttbr0_el1);



	lockdep_assert_irqs_disabled();



	/* Mirror check_and_switch_context() */

	if (system_supports_cnp())

		cpu_set_reserved_ttbr0();



	__arm64_workaround_1542418_asid_rollover();

	isb();



	write_sysreg(ttbr0, ttbr0_el1);

	isb();

}



static void flush_context(unsigned int cpu)

{

	int i;