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Commit 246e2324 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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clk: renesas: r8a77980: Correct parent clock of PCIEC0



According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of
December 22, 2017, the parent clock of the PCIe module clock on R-Car
V3H is S2D2.

Fixes: ce15783c ("clk: renesas: cpg-mssr: add R8A77980 support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 279ebbca
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