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Commit 02379d9a authored by Shefali Jain's avatar Shefali Jain Committed by David Collins
Browse files

clk: qcom: clk-rcg2: Read RCG source before calculating clk rate 



If the clock rate is set previously to hlos and enable
safe config is true. In that case we need to check the
rcg source to make sure recalc will return correct rate.
Rate calculation is done based on selected source rather
than 19.2 MHZ. Also, we are setting correct src value for
XO based on the parent map of a particular clock.

Change-Id: Id6d2923136a0848d55cff37fb5ef2e3b092af27a
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent e8c3ae02

drivers/clk/qcom/clk-rcg2.c

+36 −5
Original line number Diff line number Diff line
@@ -64,6 +64,16 @@ static struct freq_tbl cxo_f = { 
	.n = 0,

};



static void update_src_map(struct clk_hw *hw)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);

	int i, num_parents = clk_hw_get_num_parents(hw);



	for (i = 0; i < num_parents; i++)

		if (!rcg->parent_map[i].cfg)

			cxo_f.src = rcg->parent_map[i].src;

}



static int clk_rcg2_is_enabled(struct clk_hw *hw)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -248,17 +258,20 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);

	const struct freq_tbl *f_curr;

	u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;

	u32 cfg, src, hid_div, m = 0, n = 0, mode = 0, mask;



	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);

	src = cfg;

	src &= CFG_SRC_SEL_MASK;

	src >>= CFG_SRC_SEL_SHIFT;



	if (rcg->enable_safe_config && (!clk_hw_is_prepared(hw)

				|| !clk_hw_is_enabled(hw))) {

				|| !clk_hw_is_enabled(hw)) && !src) {

		if (!rcg->current_freq)

			rcg->current_freq = cxo_f.freq;

		return rcg->current_freq;

	}



	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);



	if (rcg->mnd_width) {

		mask = BIT(rcg->mnd_width) - 1;

		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
@@ -271,7 +284,7 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
		mode >>= CFG_MODE_SHIFT;

	}



	if (rcg->enable_safe_config) {

	if (rcg->enable_safe_config && !src) {

		f_curr = qcom_find_freq(rcg->freq_tbl, rcg->current_freq);

		if (!f_curr)

			return -EINVAL;
@@ -504,6 +517,12 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (!f)

		return -EINVAL;



	/*

	 * Set the correct source value for CXO as per

	 * as per defined parent map.

	 */

	update_src_map(hw);



	/*

	 * Return if the RCG is currently disabled. This configuration update

	 * will happen as part of the RCG enable sequence.
@@ -587,6 +606,12 @@ static int clk_rcg2_enable(struct clk_hw *hw) 
	unsigned long rate;

	const struct freq_tbl *f;



	/*

	 * Set the correct source value for CXO as per

	 * as per defined parent map.

	 */

	update_src_map(hw);



	if (rcg->flags & FORCE_ENABLE_RCG) {

		clk_rcg2_set_force_enable(hw);

		return 0;
@@ -628,6 +653,12 @@ static void clk_rcg2_disable(struct clk_hw *hw) 
{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);



	/*

	 * Set the correct source value for CXO as per

	 * as per defined parent map.

	 */

	update_src_map(hw);



	if (rcg->flags & FORCE_ENABLE_RCG) {

		clk_rcg2_clear_force_enable(hw);

		return;