Loading Documentation/devicetree/bindings/thermal/qcom-lmh-dcvs.txt +6 −0 Original line number Diff line number Diff line Loading @@ -25,12 +25,18 @@ Properties: interrupt generated by the LMH DCVSh hardware. LMH DCVSh hardware will generate this interrupt whenever it makes a new cpu DCVS decision. - qcom,affinity: Usage: Required Value type: <u32> Definition: Should specify the cluster affinity this hardware corresponds to. Example: lmh_dcvs0: qcom,limits-dcvs@0 { compatible = "qcom,msm-hw-limits"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; qcom,affinity = <0>; }; CPU0: cpu@0 { Loading drivers/thermal/qcom/msm_lmh_dcvs.c +4 −3 Original line number Diff line number Diff line Loading @@ -396,8 +396,6 @@ static int limits_dcvs_probe(struct platform_device *pdev) continue; lmh_node = of_parse_phandle(cpu_node, "qcom,lmh-dcvs", 0); if (lmh_node == dn) { affinity = MPIDR_AFFINITY_LEVEL( cpu_logical_map(cpu), 1); /*set the cpumask*/ cpumask_set_cpu(cpu, &(mask)); } Loading @@ -409,7 +407,7 @@ static int limits_dcvs_probe(struct platform_device *pdev) * We return error if none of the CPUs have * reference to our LMH node */ if (affinity == -1) if (cpumask_empty(&mask)) return -EINVAL; ret = limits_dcvs_get_freq_limits(cpumask_first(&mask), &max_freq, Loading @@ -426,6 +424,9 @@ static int limits_dcvs_probe(struct platform_device *pdev) return -ENOMEM; cpumask_copy(&hw->core_map, &mask); ret = of_property_read_u32(dn, "qcom,affinity", &affinity); if (ret) return -ENODEV; switch (affinity) { case 0: hw->affinity = LIMITS_CLUSTER_0; Loading Loading
Documentation/devicetree/bindings/thermal/qcom-lmh-dcvs.txt +6 −0 Original line number Diff line number Diff line Loading @@ -25,12 +25,18 @@ Properties: interrupt generated by the LMH DCVSh hardware. LMH DCVSh hardware will generate this interrupt whenever it makes a new cpu DCVS decision. - qcom,affinity: Usage: Required Value type: <u32> Definition: Should specify the cluster affinity this hardware corresponds to. Example: lmh_dcvs0: qcom,limits-dcvs@0 { compatible = "qcom,msm-hw-limits"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; qcom,affinity = <0>; }; CPU0: cpu@0 { Loading
drivers/thermal/qcom/msm_lmh_dcvs.c +4 −3 Original line number Diff line number Diff line Loading @@ -396,8 +396,6 @@ static int limits_dcvs_probe(struct platform_device *pdev) continue; lmh_node = of_parse_phandle(cpu_node, "qcom,lmh-dcvs", 0); if (lmh_node == dn) { affinity = MPIDR_AFFINITY_LEVEL( cpu_logical_map(cpu), 1); /*set the cpumask*/ cpumask_set_cpu(cpu, &(mask)); } Loading @@ -409,7 +407,7 @@ static int limits_dcvs_probe(struct platform_device *pdev) * We return error if none of the CPUs have * reference to our LMH node */ if (affinity == -1) if (cpumask_empty(&mask)) return -EINVAL; ret = limits_dcvs_get_freq_limits(cpumask_first(&mask), &max_freq, Loading @@ -426,6 +424,9 @@ static int limits_dcvs_probe(struct platform_device *pdev) return -ENOMEM; cpumask_copy(&hw->core_map, &mask); ret = of_property_read_u32(dn, "qcom,affinity", &affinity); if (ret) return -ENODEV; switch (affinity) { case 0: hw->affinity = LIMITS_CLUSTER_0; Loading