Loading drivers/gpu/msm/a6xx_reg.h +0 −1 Original line number Diff line number Diff line Loading @@ -764,7 +764,6 @@ #define PDC_GPU_TCS1_CMD0_MSGID 0x21575 #define PDC_GPU_TCS1_CMD0_ADDR 0x21576 #define PDC_GPU_TCS1_CMD0_DATA 0x21577 #define PDC_GPU_TIMESTAMP_UNIT1_EN_DRV0 0x23489 #define PDC_GPU_SEQ_MEM_0 0xA0000 #endif /* _A6XX_REG_H */ Loading drivers/gpu/msm/adreno_a6xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -1092,7 +1092,7 @@ static int a6xx_rpmh_power_off_gpu(struct kgsl_device *device) ret = a6xx_hm_sptprac_control(device, false); /* RSC sleep sequence */ _regwrite(gmu->pdc_reg_virt, PDC_GPU_TIMESTAMP_UNIT1_EN_DRV0, 1); kgsl_gmu_regwrite(device, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1); kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, 1); wmb(); Loading Loading
drivers/gpu/msm/a6xx_reg.h +0 −1 Original line number Diff line number Diff line Loading @@ -764,7 +764,6 @@ #define PDC_GPU_TCS1_CMD0_MSGID 0x21575 #define PDC_GPU_TCS1_CMD0_ADDR 0x21576 #define PDC_GPU_TCS1_CMD0_DATA 0x21577 #define PDC_GPU_TIMESTAMP_UNIT1_EN_DRV0 0x23489 #define PDC_GPU_SEQ_MEM_0 0xA0000 #endif /* _A6XX_REG_H */ Loading
drivers/gpu/msm/adreno_a6xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -1092,7 +1092,7 @@ static int a6xx_rpmh_power_off_gpu(struct kgsl_device *device) ret = a6xx_hm_sptprac_control(device, false); /* RSC sleep sequence */ _regwrite(gmu->pdc_reg_virt, PDC_GPU_TIMESTAMP_UNIT1_EN_DRV0, 1); kgsl_gmu_regwrite(device, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1); kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, 1); wmb(); Loading