clk: Add vdd_class support for handoff and use_max_uV

Some dedicated power rails do not require a max voltage vote during bootup.
Allow clock drivers to skip handoff for the corresponding VDD classes.

Multiple vdd_class structures might share same set of regulators. If the
FMAXes for these different vdd_class structures do not have the same level
vote, there could be a conflict when setting voltage on the regulator.
Add a flag use_max_uV to vote for INT_MAX as max_uV when calling
regulator_set_voltage(). Constraints in the regulator driver make sure that
the final voltage meets the requirement of that regulator's operational
range.

CRs-Fixed: 2044818
Change-Id: I15c9dc3ecf907723a136cbe90597ccafeba91af0
Signed-off-by: Taniya Das <tdas@codeaurora.org>