Merge "ARM: dts: msm: Add camera ICP devices for sdm845" into msm-4.9

		src-clock-name = "ife_clk_src";

		status = "ok";

	};

	qcom,cam-icp {

		compatible = "qcom,cam-icp";

		compat-hw-name = "qcom,a5",

			"qcom,ipe0",

			"qcom,ipe1",

			"qcom,bps";

		num-a5 = <1>;

		num-ipe = <2>;

		num-bps = <1>;

		status = "ok";

	};

	qcom,a5@ac00000 {

		cell-index = <0>;

		compatible = "qcom,cam_a5";

		reg = <0xac00000 0x6000>,

			<0xac10000 0x8000>,

			<0xac18000 0x3000>;

		reg-names = "a5_qgic", "a5_sierra", "a5_csr";

		reg-cam-base = <0x00000 0x10000 0x18000>;

		interrupts = <0 463 0>;

		interrupt-names = "a5";

		regulator-names = "camss-vdd";

		camss-vdd-supply = <&titan_top_gdsc>;

		clock-names = "gcc_cam_ahb_clk",

			"gcc_cam_axi_clk",

			"soc_ahb_clk",

			"cpas_ahb_clk",

			"camnoc_axi_clk",

			"icp_apb_clk",

			"icp_atb_clk",

			"icp_clk",

			"icp_clk_src",

			"icp_cti_clk",

			"icp_ts_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,

				<&clock_gcc GCC_CAMERA_AXI_CLK>,

				<&clock_camcc CAM_CC_SOC_AHB_CLK>,

				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

				<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

				<&clock_camcc CAM_CC_ICP_APB_CLK>,

				<&clock_camcc CAM_CC_ICP_ATB_CLK>,

				<&clock_camcc CAM_CC_ICP_CLK>,

				<&clock_camcc CAM_CC_ICP_CLK_SRC>,

				<&clock_camcc CAM_CC_ICP_CTI_CLK>,

				<&clock_camcc CAM_CC_ICP_TS_CLK>;

		clock-rates = <0 0 0 80000000 0 0 0 0 600000000 0 0>;

		fw_name = "CAMERA_ICP.elf";

		status = "ok";

	};

	qcom,ipe0 {

		cell-index = <0>;

		compatible = "qcom,cam_ipe";

		regulator-names = "ipe0-vdd";

		ipe0-vdd-supply = <&ipe_0_gdsc>;

		clock-names = "ipe_0_ahb_clk",

			"ipe_0_areg_clk",

			"ipe_0_axi_clk",

			"ipe_0_clk",

			"ipe_0_clk_src";

		clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

				<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,

				<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,

				<&clock_camcc CAM_CC_IPE_0_CLK>,

				<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;

		clock-rates = <80000000 400000000 0 0 600000000>;

		status = "ok";

	};

	qcom,ipe1 {

		cell-index = <1>;

		compatible = "qcom,cam_ipe";

		regulator-names = "ipe1-vdd";

		ipe1-vdd-supply = <&ipe_1_gdsc>;

		clock-names = "ipe_1_ahb_clk",

			"ipe_1_areg_clk",

			"ipe_1_axi_clk",

			"ipe_1_clk",

			"ipe_1_clk_src";

		clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

				<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,

				<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,

				<&clock_camcc CAM_CC_IPE_1_CLK>,

				<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;

		clock-rates = <80000000 400000000 0 0 600000000>;

		status = "ok";

	};

	qcom,bps {

		cell-index = <0>;

		compatible = "qcom,cam_bps";

		regulator-names = "bps-vdd";

		bps-vdd-supply = <&bps_gdsc>;

		clock-names = "bps_ahb_clk",

			"bps_areg_clk",

			"bps_axi_clk",

			"bps_clk",

			"bps_clk_src";

		clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,

				<&clock_camcc CAM_CC_BPS_AREG_CLK>,

				<&clock_camcc CAM_CC_BPS_AXI_CLK>,

				<&clock_camcc CAM_CC_BPS_CLK>,

				<&clock_camcc CAM_CC_BPS_CLK_SRC>;

		clock-rates = <80000000 400000000 0 0 600000000>;

		status = "ok";

	};

};