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Commit df15d3d6 authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "usb: dwc3: core: Disable internal clock gating conditionally" into msm-4.8

parents b3271e76 00b03981

Documentation/devicetree/bindings/usb/dwc3.txt

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,8 @@ Optional properties: 
 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ

	register for post-silicon frame length adjustment when the

	fladj_30mhz_sdbnd signal is invalid or incorrect.

 - snps,disable-clk-gating: If present, disable controller's internal clock

	gating. Default it is enabled.



This is usually a subnode to DWC3 glue to which it is connected.

drivers/usb/dwc3/core.c

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Original line number Diff line number Diff line
@@ -1258,6 +1258,8 @@ static int dwc3_probe(struct platform_device *pdev) 
				    &dwc->hsphy_interface);

	device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",

				 &dwc->fladj);

	dwc->disable_clk_gating = device_property_read_bool(dev,

				"snps,disable-clk-gating");



	if (dwc->enable_bus_suspend) {

		pm_runtime_set_autosuspend_delay(dev, 500);