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Commit 00b03981 authored by Mayank Rana's avatar Mayank Rana Committed by Jack Pham
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usb: dwc3: core: Disable internal clock gating conditionally 



Currently USB DWC3 controller's internal clock gating is disabled
unconditionally. In few platform, it is possible to enable internal
clock gating with controller. Hence this change adds support to
disable this functionality conditionally using "snps,disable-clk-gating"
device tree property. With this change USB controller's internal clock
gating is enabled by default.

Change-Id: I17d43a23d3bff0cb516b952c35c4a13af53f7777
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 53c1534d

Documentation/devicetree/bindings/usb/dwc3.txt

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,8 @@ Optional properties: 
 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ

	register for post-silicon frame length adjustment when the

	fladj_30mhz_sdbnd signal is invalid or incorrect.

 - snps,disable-clk-gating: If present, disable controller's internal clock

	gating. Default it is enabled.



This is usually a subnode to DWC3 glue to which it is connected.

drivers/usb/dwc3/core.c

+2 −0
Original line number Diff line number Diff line
@@ -1258,6 +1258,8 @@ static int dwc3_probe(struct platform_device *pdev) 
				    &dwc->hsphy_interface);

	device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",

				 &dwc->fladj);

	dwc->disable_clk_gating = device_property_read_bool(dev,

				"snps,disable-clk-gating");



	if (dwc->enable_bus_suspend) {

		pm_runtime_set_autosuspend_delay(dev, 500);