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Commit b3271e76 authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Enable HW clockgating and preemption for SDM660 GPU" into msm-4.8

parents 977faf45 29dd66c0

drivers/gpu/msm/adreno-gpulist.h

+2 −2
Original line number Diff line number Diff line
@@ -289,8 +289,8 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 1,

		.minor = 2,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_CPZ_RETENTION,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a512_zap",

drivers/gpu/msm/adreno_a5xx.c

+71 −2
Original line number Diff line number Diff line
@@ -194,7 +194,8 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
		/* A510 has 3 XIN ports in VBIF */

		gpudev->vbif_xin_halt_ctrl0_mask =

				A510_VBIF_XIN_HALT_CTRL0_MASK;

	} else if (adreno_is_a540(adreno_dev)) {

	} else if (adreno_is_a540(adreno_dev) ||

		adreno_is_a512(adreno_dev)) {

		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;

	}
@@ -483,7 +484,7 @@ static int a5xx_regulator_enable(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, 0x00000055);

		a5xx_hwcg_set(adreno_dev, true);

		/* Turn on sp_input_clk at HM level */

		kgsl_regrmw(device, A5XX_RBBM_CLOCK_CNTL, 3, 0);

		kgsl_regrmw(device, A5XX_RBBM_CLOCK_CNTL, 0xFF, 0);

		return 0;

	}
@@ -533,6 +534,9 @@ static void a5xx_regulator_disable(struct adreno_device *adreno_dev) 
	unsigned int reg;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (adreno_is_a512(adreno_dev))

		return;



	/* If feature is not supported or not enabled */

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) ||

		!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag)) {
@@ -1118,6 +1122,65 @@ static const struct kgsl_hwcg_reg a540_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000004}

};



static const struct kgsl_hwcg_reg a512_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

};



static const struct {

	int (*devfunc)(struct adreno_device *adreno_dev);

	const struct kgsl_hwcg_reg *regs;
@@ -1125,6 +1188,7 @@ static const struct { 
} a5xx_hwcg_registers[] = {

	{ adreno_is_a540, a540_hwcg_regs, ARRAY_SIZE(a540_hwcg_regs) },

	{ adreno_is_a530, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a512, a512_hwcg_regs, ARRAY_SIZE(a512_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

	{ adreno_is_a505, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
@@ -1868,6 +1932,11 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x20);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);

	} else if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev)) {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x40);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);

	} else {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x40);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x40);