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Commit d02444bf authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Remove certain BCR reset references on SDM845"

parents 7fe6b104 77c17178

drivers/clk/qcom/camcc-sdm845.c

+0 −11
Original line number Diff line number Diff line
@@ -1928,22 +1928,11 @@ static struct clk_regmap *cam_cc_sdm845_clocks[] = { 
};



static const struct qcom_reset_map cam_cc_sdm845_resets[] = {

	[TITAN_CAM_CC_BPS_BCR] = { 0x6000 },

	[TITAN_CAM_CC_CAMNOC_BCR] = { 0xb120 },

	[TITAN_CAM_CC_CCI_BCR] = { 0xb0d4 },

	[TITAN_CAM_CC_CPAS_BCR] = { 0xb118 },

	[TITAN_CAM_CC_CSI0PHY_BCR] = { 0x5000 },

	[TITAN_CAM_CC_CSI1PHY_BCR] = { 0x5024 },

	[TITAN_CAM_CC_CSI2PHY_BCR] = { 0x5048 },

	[TITAN_CAM_CC_FD_BCR] = { 0xb0ac },

	[TITAN_CAM_CC_ICP_BCR] = { 0xb074 },

	[TITAN_CAM_CC_IFE_0_BCR] = { 0x9000 },

	[TITAN_CAM_CC_IFE_1_BCR] = { 0xa000 },

	[TITAN_CAM_CC_IFE_LITE_BCR] = { 0xb000 },

	[TITAN_CAM_CC_IPE_0_BCR] = { 0x7000 },

	[TITAN_CAM_CC_IPE_1_BCR] = { 0x8000 },

	[TITAN_CAM_CC_JPEG_BCR] = { 0xb048 },

	[TITAN_CAM_CC_LRME_BCR] = { 0xb0f4 },

	[TITAN_CAM_CC_MCLK0_BCR] = { 0x4000 },

	[TITAN_CAM_CC_MCLK1_BCR] = { 0x4020 },

	[TITAN_CAM_CC_MCLK2_BCR] = { 0x4040 },

drivers/clk/qcom/dispcc-sdm845.c

+0 −2
Original line number Diff line number Diff line
@@ -992,8 +992,6 @@ static struct clk_regmap *disp_cc_sdm845_clocks[] = { 
};



static const struct qcom_reset_map disp_cc_sdm845_resets[] = {

	[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },

	[DISP_CC_MDSS_GCC_CLOCKS_BCR] = { 0x4000 },

	[DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },

};

drivers/clk/qcom/gcc-sdm845.c

+0 −1
Original line number Diff line number Diff line
@@ -3566,7 +3566,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
};



static const struct qcom_reset_map gcc_sdm845_resets[] = {

	[GCC_GPU_BCR] = { 0x71000 },

	[GCC_MMSS_BCR] = { 0xb000 },

	[GCC_PCIE_0_BCR] = { 0x6b000 },

	[GCC_PCIE_1_BCR] = { 0x8d000 },

drivers/clk/qcom/videocc-sdm845.c

+0 −9
Original line number Diff line number Diff line
@@ -311,13 +311,6 @@ static struct clk_regmap *video_cc_sdm845_clocks[] = { 
	[VIDEO_PLL0] = &video_pll0.clkr,

};



static const struct qcom_reset_map video_cc_sdm845_resets[] = {

	[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },

	[VIDEO_CC_VCODEC0_BCR] = { 0x870 },

	[VIDEO_CC_VCODEC1_BCR] = { 0x8b0 },

	[VIDEO_CC_VENUS_BCR] = { 0x810 },

};



static const struct regmap_config video_cc_sdm845_regmap_config = {

	.reg_bits	= 32,

	.reg_stride	= 4,
@@ -330,8 +323,6 @@ static const struct qcom_cc_desc video_cc_sdm845_desc = { 
	.config = &video_cc_sdm845_regmap_config,

	.clks = video_cc_sdm845_clocks,

	.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),

	.resets = video_cc_sdm845_resets,

	.num_resets = ARRAY_SIZE(video_cc_sdm845_resets),

};



static const struct of_device_id video_cc_sdm845_match_table[] = {

include/dt-bindings/clock/qcom,camcc-sdm845.h

+10 −21
Original line number Diff line number Diff line
@@ -102,26 +102,15 @@ 
#define CAM_CC_SOC_AHB_CLK					85

#define CAM_CC_SYS_TMR_CLK					86



#define TITAN_CAM_CC_BPS_BCR					0

#define TITAN_CAM_CC_CAMNOC_BCR					1

#define TITAN_CAM_CC_CCI_BCR					2

#define TITAN_CAM_CC_CPAS_BCR					3

#define TITAN_CAM_CC_CSI0PHY_BCR				4

#define TITAN_CAM_CC_CSI1PHY_BCR				5

#define TITAN_CAM_CC_CSI2PHY_BCR				6

#define TITAN_CAM_CC_FD_BCR					7

#define TITAN_CAM_CC_ICP_BCR					8

#define TITAN_CAM_CC_IFE_0_BCR					9

#define TITAN_CAM_CC_IFE_1_BCR					10

#define TITAN_CAM_CC_IFE_LITE_BCR				11

#define TITAN_CAM_CC_IPE_0_BCR					12

#define TITAN_CAM_CC_IPE_1_BCR					13

#define TITAN_CAM_CC_JPEG_BCR					14

#define TITAN_CAM_CC_LRME_BCR					15

#define TITAN_CAM_CC_MCLK0_BCR					16

#define TITAN_CAM_CC_MCLK1_BCR					17

#define TITAN_CAM_CC_MCLK2_BCR					18

#define TITAN_CAM_CC_MCLK3_BCR					19

#define TITAN_CAM_CC_TITAN_TOP_BCR				20

#define TITAN_CAM_CC_CCI_BCR					0

#define TITAN_CAM_CC_CPAS_BCR					1

#define TITAN_CAM_CC_CSI0PHY_BCR				2

#define TITAN_CAM_CC_CSI1PHY_BCR				3

#define TITAN_CAM_CC_CSI2PHY_BCR				4

#define TITAN_CAM_CC_MCLK0_BCR					5

#define TITAN_CAM_CC_MCLK1_BCR					6

#define TITAN_CAM_CC_MCLK2_BCR					7

#define TITAN_CAM_CC_MCLK3_BCR					8

#define TITAN_CAM_CC_TITAN_TOP_BCR				9



#endif