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Commit 7fe6b104 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gcc-sdm845: Populate the hwcg fields of branch clocks"

parents d87f8195 b1886f44

drivers/clk/qcom/gcc-sdm845.c

+66 −0
Original line number Diff line number Diff line
@@ -1240,6 +1240,8 @@ static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {

	.halt_reg = 0x82028,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x82028,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x82028,

		.enable_mask = BIT(0),
@@ -1275,6 +1277,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { 
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {

	.halt_reg = 0x82024,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x82024,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x82024,

		.enable_mask = BIT(0),
@@ -1346,6 +1350,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 
static struct clk_branch gcc_boot_rom_ahb_clk = {

	.halt_reg = 0x38004,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x38004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(10),
@@ -1359,6 +1365,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { 
static struct clk_branch gcc_camera_ahb_clk = {

	.halt_reg = 0xb008,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0xb008,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0xb008,

		.enable_mask = BIT(0),
@@ -1398,6 +1406,8 @@ static struct clk_branch gcc_camera_xo_clk = { 
static struct clk_branch gcc_ce1_ahb_clk = {

	.halt_reg = 0x4100c,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x4100c,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(3),
@@ -1504,6 +1514,8 @@ static struct clk_branch gcc_cpuss_dvm_bus_clk = { 
static struct clk_branch gcc_cpuss_gnoc_clk = {

	.halt_reg = 0x48004,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x48004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(22),
@@ -1548,6 +1560,8 @@ static struct clk_branch gcc_ddrss_gpu_axi_clk = { 
static struct clk_branch gcc_disp_ahb_clk = {

	.halt_reg = 0xb00c,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0xb00c,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0xb00c,

		.enable_mask = BIT(0),
@@ -1675,6 +1689,8 @@ static struct clk_branch gcc_gp3_clk = { 
static struct clk_branch gcc_gpu_cfg_ahb_clk = {

	.halt_reg = 0x71004,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x71004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x71004,

		.enable_mask = BIT(0),
@@ -1774,6 +1790,8 @@ static struct clk_branch gcc_mss_axis2_clk = { 
static struct clk_branch gcc_mss_cfg_ahb_clk = {

	.halt_reg = 0x8a000,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x8a000,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x8a000,

		.enable_mask = BIT(0),
@@ -1799,6 +1817,8 @@ static struct clk_gate2 gcc_mss_gpll0_div_clk_src = { 
static struct clk_branch gcc_mss_mfab_axis_clk = {

	.halt_reg = 0x8a004,

	.halt_check = BRANCH_VOTED,

	.hwcg_reg = 0x8a004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x8a004,

		.enable_mask = BIT(0),
@@ -1856,6 +1876,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { 
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {

	.halt_reg = 0x6b018,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x6b018,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(2),
@@ -1907,6 +1929,8 @@ static struct clk_gate2 gcc_pcie_0_pipe_clk = { 
static struct clk_branch gcc_pcie_0_slv_axi_clk = {

	.halt_reg = 0x6b010,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x6b010,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(0),
@@ -1951,6 +1975,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { 
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {

	.halt_reg = 0x8d018,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x8d018,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(28),
@@ -2002,6 +2028,8 @@ static struct clk_gate2 gcc_pcie_1_pipe_clk = { 
static struct clk_branch gcc_pcie_1_slv_axi_clk = {

	.halt_reg = 0x8d010,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x8d010,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(26),
@@ -2082,6 +2110,8 @@ static struct clk_branch gcc_pdm2_clk = { 
static struct clk_branch gcc_pdm_ahb_clk = {

	.halt_reg = 0x33004,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x33004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x33004,

		.enable_mask = BIT(0),
@@ -2108,6 +2138,8 @@ static struct clk_branch gcc_pdm_xo4_clk = { 
static struct clk_branch gcc_prng_ahb_clk = {

	.halt_reg = 0x34004,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x34004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(13),
@@ -2121,6 +2153,8 @@ static struct clk_branch gcc_prng_ahb_clk = { 
static struct clk_branch gcc_qmip_camera_ahb_clk = {

	.halt_reg = 0xb014,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0xb014,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0xb014,

		.enable_mask = BIT(0),
@@ -2134,6 +2168,8 @@ static struct clk_branch gcc_qmip_camera_ahb_clk = { 
static struct clk_branch gcc_qmip_disp_ahb_clk = {

	.halt_reg = 0xb018,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0xb018,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0xb018,

		.enable_mask = BIT(0),
@@ -2147,6 +2183,8 @@ static struct clk_branch gcc_qmip_disp_ahb_clk = { 
static struct clk_branch gcc_qmip_video_ahb_clk = {

	.halt_reg = 0xb010,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0xb010,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0xb010,

		.enable_mask = BIT(0),
@@ -2461,6 +2499,8 @@ static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {

	.halt_reg = 0x17008,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x17008,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(7),
@@ -2487,6 +2527,8 @@ static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {

	.halt_reg = 0x18010,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x18010,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(21),
@@ -2624,6 +2666,8 @@ static struct clk_branch gcc_tsif_ref_clk = { 
static struct clk_branch gcc_ufs_card_ahb_clk = {

	.halt_reg = 0x75010,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x75010,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x75010,

		.enable_mask = BIT(0),
@@ -2637,6 +2681,8 @@ static struct clk_branch gcc_ufs_card_ahb_clk = { 
static struct clk_branch gcc_ufs_card_axi_clk = {

	.halt_reg = 0x7500c,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x7500c,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x7500c,

		.enable_mask = BIT(0),
@@ -2685,6 +2731,8 @@ static struct clk_branch gcc_ufs_card_clkref_clk = { 
static struct clk_branch gcc_ufs_card_ice_core_clk = {

	.halt_reg = 0x75058,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x75058,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x75058,

		.enable_mask = BIT(0),
@@ -2720,6 +2768,8 @@ static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { 
static struct clk_branch gcc_ufs_card_phy_aux_clk = {

	.halt_reg = 0x7508c,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x7508c,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x7508c,

		.enable_mask = BIT(0),
@@ -2791,6 +2841,8 @@ static struct clk_gate2 gcc_ufs_card_tx_symbol_0_clk = { 
static struct clk_branch gcc_ufs_card_unipro_core_clk = {

	.halt_reg = 0x75054,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x75054,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x75054,

		.enable_mask = BIT(0),
@@ -2839,6 +2891,8 @@ static struct clk_branch gcc_ufs_mem_clkref_clk = { 
static struct clk_branch gcc_ufs_phy_ahb_clk = {

	.halt_reg = 0x77010,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x77010,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x77010,

		.enable_mask = BIT(0),
@@ -2852,6 +2906,8 @@ static struct clk_branch gcc_ufs_phy_ahb_clk = { 
static struct clk_branch gcc_ufs_phy_axi_clk = {

	.halt_reg = 0x7700c,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x7700c,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x7700c,

		.enable_mask = BIT(0),
@@ -2887,6 +2943,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 
static struct clk_branch gcc_ufs_phy_ice_core_clk = {

	.halt_reg = 0x77058,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x77058,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x77058,

		.enable_mask = BIT(0),
@@ -2922,6 +2980,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {

	.halt_reg = 0x7708c,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x7708c,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x7708c,

		.enable_mask = BIT(0),
@@ -2993,6 +3053,8 @@ static struct clk_gate2 gcc_ufs_phy_tx_symbol_0_clk = { 
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {

	.halt_reg = 0x77054,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x77054,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x77054,

		.enable_mask = BIT(0),
@@ -3248,6 +3310,8 @@ static struct clk_gate2 gcc_usb3_sec_phy_pipe_clk = { 
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {

	.halt_reg = 0x6a004,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x6a004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x6a004,

		.enable_mask = BIT(0),
@@ -3261,6 +3325,8 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 
static struct clk_branch gcc_video_ahb_clk = {

	.halt_reg = 0xb004,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0xb004,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0xb004,

		.enable_mask = BIT(0),