mmc: sdhci: Poll for register status much tightly

On fast path, waiting for 1ms interval to poll registers cause
performance degradation. Also having 1ms delays for polling with
interrupts disabled cause considerable system latencies, hence
poll at 1us interval.

Change-Id: I40113ccf56050b3c46604112846e9b37b254d2be
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[xiaonian@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Xiaonian Wang <xiaonian@codeaurora.org>