PCI/ASPM: Add L1 substate capability structure register definitions

Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

Change-Id: I9b4c162da8ff901746bebfe9812badefd76e30dd
[bhelgaas: add PCIe spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Git-commit: 0fc1223f0e77a748f7040562faaa7027f7db71ca
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: Tony Truong <truong@codeaurora.org>