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Commit be82c005 authored by Rajat Jain's avatar Rajat Jain Committed by Gerrit - the friendly Code Review server
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PCI/ASPM: Add L1 substate capability structure register definitions 



Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

Change-Id: I9b4c162da8ff901746bebfe9812badefd76e30dd
[bhelgaas: add PCIe spec reference]
Signed-off-by: default avatarRajat Jain <rajatja@google.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Git-commit: 0fc1223f0e77a748f7040562faaa7027f7db71ca
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 1a60f3f6

include/uapi/linux/pci_regs.h

+16 −0
Original line number Diff line number Diff line
@@ -674,6 +674,7 @@ 
#define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */

#define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */

#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */

#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */

#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
@@ -977,4 +978,19 @@ 
#define  PCI_PTM_CTRL_ENABLE		0x00000001  /* PTM enable */

#define  PCI_PTM_CTRL_ROOT		0x00000002  /* Root select */



/* L1 PM Substates */

#define PCI_L1SS_CAP		    4	/* capability register */

#define  PCI_L1SS_CAP_PCIPM_L1_2	 1	/* PCI PM L1.2 Support */

#define  PCI_L1SS_CAP_PCIPM_L1_1	 2	/* PCI PM L1.1 Support */

#define  PCI_L1SS_CAP_ASPM_L1_2		 4	/* ASPM L1.2 Support */

#define  PCI_L1SS_CAP_ASPM_L1_1		 8	/* ASPM L1.1 Support */

#define  PCI_L1SS_CAP_L1_PM_SS		16	/* L1 PM Substates Support */

#define PCI_L1SS_CTL1		    8	/* Control Register 1 */

#define  PCI_L1SS_CTL1_PCIPM_L1_2	1	/* PCI PM L1.2 Enable */

#define  PCI_L1SS_CTL1_PCIPM_L1_1	2	/* PCI PM L1.1 Support */

#define  PCI_L1SS_CTL1_ASPM_L1_2	4	/* ASPM L1.2 Support */

#define  PCI_L1SS_CTL1_ASPM_L1_1	8	/* ASPM L1.1 Support */

#define  PCI_L1SS_CTL1_L1SS_MASK	0x0000000F

#define PCI_L1SS_CTL2		    0xC	/* Control Register 2 */



#endif /* LINUX_PCI_REGS_H */