Merge "ARM: dts: msm: Add GDSC, GCC and CPU nodes for msm8953"

Qualcomm Technologies MSM Clock controller

Qualcomm Technologies MSM Clock controller devices contain PLLs, root clock

generators and other clocking hardware blocks that provide stable, low power

clocking to hardware blocks on Qualcomm Technologies SOCs. The clock controller

device node lists the power supplies needed to be scaled using the vdd_*-supply

property.

Minor differences between hardware revisions are handled in code by re-using

the compatible string to indicate the revision.

Required properties:

- compatible:           Must be one of following,

			"qcom,gcc-8953"

			"qcom,cc-debug-8953"

			"qcom,gcc-mdss-8953"

                        "qcom,gcc-gfx-8953"

                        "qcom,gcc-gfx-sdm450"

- reg:                  Pairs of physical base addresses and region sizes of

                        memory mapped registers.

- reg-names:            Names of the bases for the above registers. Currently,

                        there is one expected base: "cc_base". Optional

                        reg-names are "apcs_base", "meas", "mmss_base",

                        "lpass_base", "apcs_c0_base", "apcs_c1_base",

                        "apcs_cci_base", "efuse".

Optional properties:

- vdd_dig-supply:       The digital logic rail supply.

- <pll>_dig-supply:     Some PLLs might have separate digital supply on some

                        targets. These properties will be provided on those

                        targets for specific PLLs.

- <pll>_analog-supply:  Some PLLs might have separate analog supply on some

                        targets. These properties will be provided on those

                        targets for specific PLLs.

- vdd_gpu_mx-supply:    MX rail supply for the GPU core.

- #clock_cells:         If this device will also be providing controllable

                        clocks, the clock_cells property needs to be specified.

                        This will allow the common clock device tree framework

                        to recognize _this_ device node as a clock provider.

- qcom,<clk>-corner-<vers>: List of frequency voltage pairs that the clock can

                            operate at. Drivers can use the OPP library API to

                            operate on the list of OPPs registered using these

                            values.

- qcom,<clk>-speedbinX: A table of frequency (Hz) to voltage (corner) mapping

                        that represents the max frequency possible for each

                        supported voltage level for the clock.

                        'X' is the speed bin into which the device falls into -

                        a bin will have unique frequency-voltage relationships.

                        The value 'X' is read from efuse registers, and the right

                        table is picked from multiple possible tables.

- qcom,<clock-name>-opp-handle: phandle references to the devices for which OPP

                        table is filled with the clock frequency and voltage

                        values.

- qcom,<clock-name>-opp-store-vcorner: phandle references to the devices for

                        which OPP table is filled with the clock frequency

                         and voltage corner/level.

Example:

        clock_gcc: qcom,gcc@fc400000 {

                compatible = "qcom,gcc-8974";

                reg = <0xfc400000 0x4000>;

                reg-names = "cc_base";

                vdd_dig-supply = <&pm8841_s2_corner>;

                #clock-cells = <1>;

        };

Qualcomm Technologies MSM8953 CPU clock tree

clock-cpu-8953 is a device that represents the MSM8953 CPU subystem clock

tree. It lists the various power supplies that need to be scaled when the

clocks are scaled and also other HW specific parameters like fmax tables etc.

The root clock generator could have the ramp controller in built.

Ramp control will allow programming the sequence ID for pulse swallowing,

enable sequence and for linking sequence IDs.

Required properties:

- compatible:		Must be "qcom,clock-cpu-8953".

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Expected

			bases are:

			"c0-pll", "c1-pll", "c0-mux", "c1-mux", "cci-mux",

			"efuse", "perf_base"(optional), "rcgwr-c0-base(optional)",

			"rcgwr-c1-base(optional)".

- clocks:		The clocks sources used by the cluster/cci mux.

- clock-names:		Name of the clocks for the above clocks.

- vdd-mx-supply:	The regulator powering all the PLLs of clusters & cci.

- vdd-cl-supply:	The regulator powering the clusters & cci.

- qcom,speedX-bin-vY-ZZZ:

			A table of CPU frequency (Hz) to voltage (corner)

			mapping that represents the max frequency possible

			for each supported voltage level for a CPU. 'X' is

			the speed bin into which the device falls into - a

			bin will have unique frequency-voltage relationships.

			'Y' is the characterization version, implying that

			characterization (deciding what speed bin a device

			falls into) methods and/or encoding may change. The

			values 'X' and 'Y' are read from efuse registers, and

			the right table is picked from multiple possible tables.

			'ZZZ' can be cl for(c0 & c1) or cci depending on whether

			the table for the clusters or cci.

Optional Properties:

- qcom,enable-qos:      Boolean property to indicate the pm qos is required

			during set rate of the cluster clocks, which would not

			allow the cluster cores to go to low power mode.

Example:

	clock_cpu: qcom,cpu-clock-8953@b116000 {

		compatible = "qcom,cpu-clock-8953";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a412c  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pm8953_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			<          0 0>,

			< 2208000000 7>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  883200000 7>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

	select PINCTRL

	select QCOM_SCM if SMP

	select PM_DEVFREQ

	select COMMON_CLK

	select COMMON_CLK_QCOM

	select QCOM_GDSC

	select CLKDEV_LOOKUP

	select HAVE_CLK

	select HAVE_CLK_PREPARE

	select COMMON_CLK_MSM

config ARCH_SDM450

	bool "Enable support for SDM450"

	select PINCTRL

	select QCOM_SCM if SMP

	select PM_DEVFREQ

	select COMMON_CLK

	select COMMON_CLK_QCOM

	select QCOM_GDSC

	select CLKDEV_LOOKUP

	select HAVE_CLK

	select HAVE_CLK_PREPARE

	select COMMON_CLK_MSM

endmenu

endif

	select ARM_PSCI_FW

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select COMMON_CLK

	select COMMON_CLK if !ARCH_QCOM

	select CPU_PM if (SUSPEND || CPU_IDLE)

	select DCACHE_WORD_ACCESS

	select EDAC_SUPPORT

config ARCH_QCOM

	bool "Qualcomm Platforms"

	select PINCTRL

	select CLKDEV_LOOKUP

	select HAVE_CLK

	select HAVE_CLK_PREPARE

	select SOC_BUS

	select PM_OPP

	select MFD_CORE

config ARCH_MSM8953

	bool "Enable Support for Qualcomm Technologies Inc. MSM8953"

	depends on ARCH_QCOM

	select COMMON_CLK_QCOM

	select QCOM_GDSC

	select CPU_FREQ_QCOM

	select COMMON_CLK_MSM

	help

	  This enables support for the MSM8953 chipset. If you do not

	  wish to build a kernel that runs on this chipset, say 'N' here.

config ARCH_SDM450

	bool "Enable Support for Qualcomm Technologies Inc. SDM450"

	depends on ARCH_QCOM

	select COMMON_CLK_QCOM

	select QCOM_GDSC

	select CPU_FREQ_QCOM

	select COMMON_CLK_MSM

	help

	  This enables support for the sdm450 chipset. If you do not

	  wish to build a kernel that runs on this chipset, say 'N' here.