Loading Documentation/devicetree/bindings/clock/qcom,msm-clock-controller.txt 0 → 100644 +22 −0 Original line number Diff line number Diff line Qualcomm Technologies MSM Clock Controller Required properties : - compatible : shall contain "qcom,msm-clock-controller" - reg : shall contain base register location and length - reg-names: names of registers listed in the same order as in the reg property. - #clock-cells : shall contain 1 - #reset-cells : shall contain 1 Optional properties : - vdd_<rail>-supply: The logic rail supply. Example: clock_gcc: qcom,gcc@1800000 { compatible = "qcom,msm-clock-controller"; reg = <0x1800000 0x80000>; reg-names = "cc-base"; #clock-cells = <1>; clock-names = "a7_debug_clk"; clocks = <&clock_a7pll clk_a7_debug_mux>; }; drivers/clk/Kconfig +2 −0 Original line number Diff line number Diff line Loading @@ -212,3 +212,5 @@ source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" endmenu source "drivers/clk/msm/Kconfig" drivers/clk/Makefile +2 −1 Original line number Diff line number Diff line # common clock types obj-$(CONFIG_HAVE_CLK) += clk-devres.o obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o obj-$(CONFIG_OF) += clk.o obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o Loading Loading @@ -92,3 +92,4 @@ obj-$(CONFIG_X86) += x86/ endif obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_ARCH_QCOM) += msm/ drivers/clk/clk.c +36 −21 Original line number Diff line number Diff line Loading @@ -32,6 +32,8 @@ #include "clk.h" #if defined(CONFIG_COMMON_CLK) static DEFINE_SPINLOCK(enable_lock); static DEFINE_MUTEX(prepare_lock); Loading Loading @@ -4032,6 +4034,8 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb) } EXPORT_SYMBOL_GPL(clk_notifier_unregister); #endif /* CONFIG_COMMON_CLK */ #ifdef CONFIG_OF /** * struct of_clk_provider - Clock provider registration structure Loading Loading @@ -4069,6 +4073,8 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) } EXPORT_SYMBOL_GPL(of_clk_hw_simple_get); #if defined(CONFIG_COMMON_CLK) struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data) { struct clk_onecell_data *clk_data = data; Loading Loading @@ -4098,6 +4104,29 @@ of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) } EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get); #endif /* CONFIG_COMMON_CLK */ /** * of_clk_del_provider() - Remove a previously registered clock provider * @np: Device node pointer associated with clock provider */ void of_clk_del_provider(struct device_node *np) { struct of_clk_provider *cp; mutex_lock(&of_clk_mutex); list_for_each_entry(cp, &of_clk_providers, link) { if (cp->node == np) { list_del(&cp->link); of_node_put(cp->node); kfree(cp); break; } } mutex_unlock(&of_clk_mutex); } EXPORT_SYMBOL_GPL(of_clk_del_provider); /** * of_clk_add_provider() - Register a clock provider for a node * @np: Device node pointer associated with clock provider Loading Loading @@ -4168,27 +4197,6 @@ int of_clk_add_hw_provider(struct device_node *np, } EXPORT_SYMBOL_GPL(of_clk_add_hw_provider); /** * of_clk_del_provider() - Remove a previously registered clock provider * @np: Device node pointer associated with clock provider */ void of_clk_del_provider(struct device_node *np) { struct of_clk_provider *cp; mutex_lock(&of_clk_mutex); list_for_each_entry(cp, &of_clk_providers, link) { if (cp->node == np) { list_del(&cp->link); of_node_put(cp->node); kfree(cp); break; } } mutex_unlock(&of_clk_mutex); } EXPORT_SYMBOL_GPL(of_clk_del_provider); static struct clk_hw * __of_clk_get_hw_from_provider(struct of_clk_provider *provider, struct of_phandle_args *clkspec) Loading Loading @@ -4317,8 +4325,10 @@ const char *of_clk_get_parent_name(struct device_node *np, int index) else clk_name = NULL; } else { #if defined(CONFIG_COMMON_CLK) clk_name = __clk_get_name(clk); clk_put(clk); #endif } } Loading Loading @@ -4349,6 +4359,8 @@ int of_clk_parent_fill(struct device_node *np, const char **parents, } EXPORT_SYMBOL_GPL(of_clk_parent_fill); #if defined(CONFIG_COMMON_CLK) struct clock_provider { of_clk_init_cb_t clk_init_cb; struct device_node *np; Loading Loading @@ -4499,4 +4511,7 @@ void __init of_clk_init(const struct of_device_id *matches) force = true; } } #endif /* CONFIG_COMMON_CLK */ #endif drivers/clk/clk.h +1 −1 Original line number Diff line number Diff line Loading @@ -12,7 +12,7 @@ struct clk_hw; struct clk_core; #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) #if defined(CONFIG_OF) struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec, const char *dev_id, const char *con_id); #endif Loading Loading
Documentation/devicetree/bindings/clock/qcom,msm-clock-controller.txt 0 → 100644 +22 −0 Original line number Diff line number Diff line Qualcomm Technologies MSM Clock Controller Required properties : - compatible : shall contain "qcom,msm-clock-controller" - reg : shall contain base register location and length - reg-names: names of registers listed in the same order as in the reg property. - #clock-cells : shall contain 1 - #reset-cells : shall contain 1 Optional properties : - vdd_<rail>-supply: The logic rail supply. Example: clock_gcc: qcom,gcc@1800000 { compatible = "qcom,msm-clock-controller"; reg = <0x1800000 0x80000>; reg-names = "cc-base"; #clock-cells = <1>; clock-names = "a7_debug_clk"; clocks = <&clock_a7pll clk_a7_debug_mux>; };
drivers/clk/Kconfig +2 −0 Original line number Diff line number Diff line Loading @@ -212,3 +212,5 @@ source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" endmenu source "drivers/clk/msm/Kconfig"
drivers/clk/Makefile +2 −1 Original line number Diff line number Diff line # common clock types obj-$(CONFIG_HAVE_CLK) += clk-devres.o obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o obj-$(CONFIG_OF) += clk.o obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o Loading Loading @@ -92,3 +92,4 @@ obj-$(CONFIG_X86) += x86/ endif obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_ARCH_QCOM) += msm/
drivers/clk/clk.c +36 −21 Original line number Diff line number Diff line Loading @@ -32,6 +32,8 @@ #include "clk.h" #if defined(CONFIG_COMMON_CLK) static DEFINE_SPINLOCK(enable_lock); static DEFINE_MUTEX(prepare_lock); Loading Loading @@ -4032,6 +4034,8 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb) } EXPORT_SYMBOL_GPL(clk_notifier_unregister); #endif /* CONFIG_COMMON_CLK */ #ifdef CONFIG_OF /** * struct of_clk_provider - Clock provider registration structure Loading Loading @@ -4069,6 +4073,8 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) } EXPORT_SYMBOL_GPL(of_clk_hw_simple_get); #if defined(CONFIG_COMMON_CLK) struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data) { struct clk_onecell_data *clk_data = data; Loading Loading @@ -4098,6 +4104,29 @@ of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) } EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get); #endif /* CONFIG_COMMON_CLK */ /** * of_clk_del_provider() - Remove a previously registered clock provider * @np: Device node pointer associated with clock provider */ void of_clk_del_provider(struct device_node *np) { struct of_clk_provider *cp; mutex_lock(&of_clk_mutex); list_for_each_entry(cp, &of_clk_providers, link) { if (cp->node == np) { list_del(&cp->link); of_node_put(cp->node); kfree(cp); break; } } mutex_unlock(&of_clk_mutex); } EXPORT_SYMBOL_GPL(of_clk_del_provider); /** * of_clk_add_provider() - Register a clock provider for a node * @np: Device node pointer associated with clock provider Loading Loading @@ -4168,27 +4197,6 @@ int of_clk_add_hw_provider(struct device_node *np, } EXPORT_SYMBOL_GPL(of_clk_add_hw_provider); /** * of_clk_del_provider() - Remove a previously registered clock provider * @np: Device node pointer associated with clock provider */ void of_clk_del_provider(struct device_node *np) { struct of_clk_provider *cp; mutex_lock(&of_clk_mutex); list_for_each_entry(cp, &of_clk_providers, link) { if (cp->node == np) { list_del(&cp->link); of_node_put(cp->node); kfree(cp); break; } } mutex_unlock(&of_clk_mutex); } EXPORT_SYMBOL_GPL(of_clk_del_provider); static struct clk_hw * __of_clk_get_hw_from_provider(struct of_clk_provider *provider, struct of_phandle_args *clkspec) Loading Loading @@ -4317,8 +4325,10 @@ const char *of_clk_get_parent_name(struct device_node *np, int index) else clk_name = NULL; } else { #if defined(CONFIG_COMMON_CLK) clk_name = __clk_get_name(clk); clk_put(clk); #endif } } Loading Loading @@ -4349,6 +4359,8 @@ int of_clk_parent_fill(struct device_node *np, const char **parents, } EXPORT_SYMBOL_GPL(of_clk_parent_fill); #if defined(CONFIG_COMMON_CLK) struct clock_provider { of_clk_init_cb_t clk_init_cb; struct device_node *np; Loading Loading @@ -4499,4 +4511,7 @@ void __init of_clk_init(const struct of_device_id *matches) force = true; } } #endif /* CONFIG_COMMON_CLK */ #endif
drivers/clk/clk.h +1 −1 Original line number Diff line number Diff line Loading @@ -12,7 +12,7 @@ struct clk_hw; struct clk_core; #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) #if defined(CONFIG_OF) struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec, const char *dev_id, const char *con_id); #endif Loading