Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 44e24ad8 authored by Shefali Jain's avatar Shefali Jain
Browse files

ARM: dts: msm: Add GDSC, GCC and CPU nodes for msm8953 



Add GCC and CPU device tree nodes to support GCC and CPU
drivers. Also add GDSCs device tree nodes.

Change-Id: I32d779b04953116adaef9059a7a746441d88691b
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 8786b3d5

arch/arm64/boot/dts/qcom/msm-gdsc-8916.dtsi

0 → 100644
+91 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2015, 2017 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	gdsc_venus: qcom,gdsc@184c018 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus";

		reg = <0x184c018 0x4>;

		status = "disabled";

	};



	gdsc_mdss: qcom,gdsc@184d078 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_mdss";

		reg = <0x184d078 0x4>;

		status = "disabled";

	};



	gdsc_jpeg: qcom,gdsc@185701c {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_jpeg";

		reg = <0x185701c 0x4>;

		status = "disabled";

	};



	gdsc_vfe: qcom,gdsc@1858034 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_vfe";

		reg = <0x1858034 0x4>;

		status = "disabled";

	};



	gdsc_vfe1: qcom,gdsc@185806c {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_vfe1";

		reg = <0x185806c 0x4>;

		status = "disabled";

	};



	gdsc_cpp: qcom,gdsc@1858078 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_cpp";

		reg = <0x1858078 0x4>;

		status = "disabled";

	};



	gdsc_oxili_gx: qcom,gdsc@185901c {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_oxili_gx";

		reg = <0x185901c 0x4>;

		status = "disabled";

	};



	gdsc_venus_core0: qcom,gdsc@184c028 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus_core0";

		reg = <0x184c028 0x4>;

		status = "disabled";

	};



	gdsc_venus_core1: qcom,gdsc@184c030 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus_core1";

		reg = <0x184c030 0x4>;

		status = "disabled";

	};



	gdsc_oxili_cx: qcom,gdsc@185904c {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_oxili_cx";

		reg = <0x185904c 0x4>;

		status = "disabled";

	};



	gdsc_usb30: qcom,gdsc@183f078 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_usb30";

		reg = <0x183f078 0x4>;

		status = "disabled";

	};

};

arch/arm64/boot/dts/qcom/msm8953.dtsi

+205 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <dt-bindings/spmi/spmi.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

#include <dt-bindings/clock/msm-clocks-8953.h>



/ {

	model = "Qualcomm Technologies, Inc. MSM 8953";
@@ -293,6 +294,134 @@ 
		status = "disabled";

	};



	clock_gcc: qcom,gcc@1800000 {

		compatible = "qcom,gcc-8953";

		reg = <0x1800000 0x80000>,

			 <0x00a4124 0x08>;

		reg-names = "cc_base", "efuse";

		vdd_dig-supply = <&pm8953_s2_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_debug: qcom,cc-debug@1874000 {

		compatible = "qcom,cc-debug-8953";

		reg = <0x1874000 0x4>;

		reg-names = "cc_base";

		clocks = <&clock_cpu clk_cpu_debug_pri_mux>;

		clock-names = "debug_cpu_clk";

		#clock-cells = <1>;

	};



	clock_gcc_gfx: qcom,gcc-gfx@1800000 {

		compatible = "qcom,gcc-gfx-8953";

		reg = <0x1800000 0x80000>;

		reg-names = "cc_base";

		vdd_gfx-supply = <&gfx_vreg_corner>;

		qcom,gfxfreq-corner =

			 <         0   0 >,

			 < 133330000   1 >,  /* Min SVS   */

			 < 216000000   2 >,  /* Low SVS   */

			 < 320000000   3 >,  /* SVS       */

			 < 400000000   4 >,  /* SVS Plus  */

			 < 510000000   5 >,  /* NOM       */

			 < 560000000   6 >,  /* Nom Plus  */

			 < 650000000   7 >;  /* Turbo     */

		#clock-cells = <1>;

	};



	clock_cpu: qcom,cpu-clock-8953@b116000 {

		compatible = "qcom,cpu-clock-8953";

		reg =	 <0xb114000  0x68>,

			 <0xb014000  0x68>,

			 <0xb116000  0x400>,

			 <0xb111050  0x08>,

			 <0xb011050  0x08>,

			 <0xb1d1050  0x08>,

			 <0x00a4124  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

				"c0-pll", "c0-mux", "c1-mux",

				"cci-mux", "efuse";

		vdd-mx-supply = <&pm8953_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			<          0 0>,

			<  652800000 1>,

			< 1036800000 2>,

			< 1401600000 3>,

			< 1689600000 4>,

			< 1804800000 5>,

			< 1958400000 6>,

			< 2016000000 7>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  261120000 1>,

			<  414720000 2>,

			<  560640000 3>,

			<  675840000 4>,

			<  721920000 5>,

			<  783360000 6>,

			<  806400000 7>;

		qcom,speed2-bin-v0-cl =

			<          0 0>,

			<  652800000 1>,

			< 1036800000 2>,

			< 1401600000 3>,

			< 1689600000 4>,

			< 1804800000 5>,

			< 1958400000 6>,

			< 2016000000 7>;

		qcom,speed2-bin-v0-cci =

			<          0 0>,

			<  261120000 1>,

			<  414720000 2>,

			<  560640000 3>,

			<  675840000 4>,

			<  721920000 5>,

			<  783360000 6>,

			<  806400000 7>;

		qcom,speed7-bin-v0-cl =

			<          0 0>,

			<  652800000 1>,

			< 1036800000 2>,

			< 1401600000 3>,

			< 1689600000 4>,

			< 1804800000 5>,

			< 1958400000 6>,

			< 2016000000 7>,

			< 2150400000 8>,

			< 2208000000 9>;

		qcom,speed7-bin-v0-cci =

			<          0 0>,

			<  261120000 1>,

			<  414720000 2>,

			<  560640000 3>,

			<  675840000 4>,

			<  721920000 5>,

			<  783360000 6>,

			<  806400000 7>,

			<  860160000 8>,

			<  883200000 9>;

		qcom,speed6-bin-v0-cl =

			<          0 0>,

			<  652800000 1>,

			< 1036800000 2>,

			< 1401600000 3>,

			< 1689600000 4>,

			< 1804800000 5>;

		qcom,speed6-bin-v0-cci =

			<          0 0>,

			<  261120000 1>,

			<  414720000 2>,

			<  560640000 3>,

			<  675840000 4>,

			<  721920000 5>;

		#clock-cells = <1>;

	};



	cpubw: qcom,cpubw {

		compatible = "qcom,devbw";

		governor = "cpufreq";
@@ -775,3 +904,79 @@ 
#include "pm8953-rpm-regulator.dtsi"

#include "pm8953.dtsi"

#include "msm8953-regulator.dtsi"

#include "msm-gdsc-8916.dtsi"



&gdsc_venus {

	clock-names = "bus_clk", "core_clk";

	clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,

		<&clock_gcc clk_gcc_venus0_vcodec0_clk>;

	status = "okay";

};



&gdsc_venus_core0 {

	qcom,support-hw-trigger;

	clock-names ="core0_clk";

	clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;

	status = "okay";

};



&gdsc_mdss {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,

		<&clock_gcc clk_gcc_mdss_axi_clk>;

	proxy-supply = <&gdsc_mdss>;

	qcom,proxy-consumer-enable;

	status = "okay";

};



&gdsc_oxili_gx {

	clock-names = "core_root_clk";

	clocks =<&clock_gcc_gfx clk_gfx3d_clk_src>;

	qcom,force-enable-root-clk;

	parent-supply = <&gfx_vreg_corner>;

	status = "okay";

};



&gdsc_jpeg {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,

		<&clock_gcc clk_gcc_camss_jpeg_axi_clk>;

	status = "okay";

};



&gdsc_vfe {

	clock-names = "core_clk", "bus_clk", "micro_clk",

				"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,

		<&clock_gcc clk_gcc_camss_vfe_axi_clk>,

		<&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		<&clock_gcc clk_gcc_camss_csi_vfe0_clk>;

	status = "okay";

};



&gdsc_vfe1 {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>,

		<&clock_gcc clk_gcc_camss_vfe1_axi_clk>,

		<&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		<&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

	status = "okay";

};



&gdsc_cpp {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_cpp_clk>,

		<&clock_gcc clk_gcc_camss_cpp_axi_clk>;

	status = "okay";

};



&gdsc_oxili_cx {

	clock-names = "core_clk";

	clocks = <&clock_gcc_gfx clk_gcc_oxili_gfx3d_clk>;

	status = "okay";

};



&gdsc_usb30 {

	status = "okay";

};