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Commit acf1ef45 authored by Shrenuj Bansal's avatar Shrenuj Bansal
Browse files

msm: kgsl: Add initial A6XX device support 



Create the basic framework for the A6xx hardware layer in KGSL.
Add basic A6xx initialization sequence, which includes loading
the firmware, a number of register writes and CP init. Also,
add the interrupts and handlers for A6x.

Change-Id: Ic723506e9659b82c708a739ceb12d78cbeec2feb
Signed-off-by: default avatarShrenuj Bansal <shrenujb@codeaurora.org>
parent a9ae9de2

drivers/gpu/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ msm_adreno-y += \ 
	adreno_a3xx.o \

	adreno_a4xx.o \

	adreno_a5xx.o \

	adreno_a6xx.o \

	adreno_a3xx_snapshot.o \

	adreno_a4xx_snapshot.o \

	adreno_a5xx_snapshot.o \

drivers/gpu/msm/a6xx_reg.h

0 → 100644
+148 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef _A6XX_REG_H

#define _A6XX_REG_H



/* A6XX interrupt bits */

#define A6XX_INT_RBBM_GPU_IDLE          0

#define A6XX_INT_CP_AHB_ERROR           1

#define A6XX_INT_ATB_ASYNCFIFO_OVERFLOW 6

#define A6XX_INT_RBBM_GPC_ERROR         7

#define A6XX_INT_CP_SW                  8

#define A6XX_INT_CP_HW_ERROR            9

#define A6XX_INT_CP_CCU_FLUSH_DEPTH_TS  10

#define A6XX_INT_CP_CCU_FLUSH_COLOR_TS  11

#define A6XX_INT_CP_CCU_RESOLVE_TS      12

#define A6XX_INT_CP_IB2                 13

#define A6XX_INT_CP_IB1                 14

#define A6XX_INT_CP_RB                  15

#define A6XX_INT_CP_RB_DONE_TS          17

#define A6XX_INT_CP_WT_DONE_TS          18

#define A6XX_INT_CP_CACHE_FLUSH_TS      20

#define A6XX_INT_RBBM_ATB_BUS_OVERFLOW  22

#define A6XX_INT_RBBM_HANG_DETECT       23

#define A6XX_INT_UCHE_OOB_ACCESS        24

#define A6XX_INT_UCHE_TRAP_INTR         25

#define A6XX_INT_DEBBUS_INTR_0          26

#define A6XX_INT_DEBBUS_INTR_1          27

#define A6XX_INT_ISDB_CPU_IRQ           30

#define A6XX_INT_ISDB_UNDER_DEBUG       31



/* CP Interrupt bits */

#define A6XX_CP_OPCODE_ERROR                    0

#define A6XX_CP_UCODE_ERROR                     1

#define A6XX_CP_HW_FAULT_ERROR                  2

#define A6XX_CP_REGISTER_PROTECTION_ERROR       4

#define A6XX_CP_AHB_ERROR                       5

#define A6XX_CP_VSD_PARITY_ERROR                6

#define A6XX_CP_ILLEGAL_INSTR_ERROR             7



/* CP registers */

#define A6XX_CP_RB_BASE                  0x800

#define A6XX_CP_RB_BASE_HI               0x801

#define A6XX_CP_RB_CNTL                  0x802

#define A6XX_CP_RB_RPTR_ADDR_LO          0x804

#define A6XX_CP_RB_RPTR_ADDR_HI          0x805

#define A6XX_CP_RB_RPTR                  0x806

#define A6XX_CP_RB_WPTR                  0x807

#define A6XX_CP_SQE_CNTL                 0x808

#define A6XX_CP_HW_FAULT                 0x821

#define A6XX_CP_INTERRUPT_STATUS         0x823

#define A6XX_CP_PROTECT_STATUS           0X824

#define A6XX_CP_SQE_INSTR_BASE_LO        0x830

#define A6XX_CP_SQE_INSTR_BASE_HI        0x831

#define A6XX_CP_MISC_CNTL                0x840

#define A6XX_CP_ROQ_THRESHOLDS_1         0x8C1

#define A6XX_CP_ROQ_THRESHOLDS_2         0x8C2

#define A6XX_CP_MEM_POOL_SIZE            0x8C3

#define A6XX_CP_CHICKEN_DBG              0x841

#define A6XX_CP_ADDR_MODE_CNTL           0x842

#define A6XX_CP_PROTECT_CNTL             0x84F

#define A6XX_CP_PROTECT_REG              0x850

#define A6XX_CP_ALWAYS_ON_COUNTER_LO     0x980

#define A6XX_CP_ALWAYS_ON_COUNTER_HI     0x981

#define A6XX_CP_AHB_CNTL                 0x98D

#define A6XX_VSC_ADDR_MODE_CNTL          0xC01



/* RBBM registers */

#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL           0x10

#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL        0x1f

#define A6XX_RBBM_INT_CLEAR_CMD                  0x37

#define A6XX_RBBM_INT_0_MASK                     0x38

#define A6XX_RBBM_SW_RESET_CMD                   0x43

#define A6XX_RBBM_BLOCK_SW_RESET_CMD             0x45

#define A6XX_RBBM_BLOCK_SW_RESET_CMD2            0x46

#define A6XX_RBBM_CLOCK_CNTL                     0xAE

#define A6XX_RBBM_INT_0_STATUS                   0x201

#define A6XX_RBBM_STATUS                         0x210

#define A6XX_RBBM_STATUS3                        0x213

#define A6XX_RBBM_SECVID_TRUST_CNTL              0xF400

#define A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL      0xF810



/* VSC registers */

#define A6XX_GRAS_ADDR_MODE_CNTL            0x8601



/* RB registers */

#define A6XX_RB_ADDR_MODE_CNTL              0x8E05

#define A6XX_RB_NC_MODE_CNTL                0x8E08



/* PC registers */

#define A6XX_PC_DBG_ECO_CNTL                0x9E00

#define A6XX_PC_ADDR_MODE_CNTL              0x9E01



/* HLSQ registers */

#define A6XX_HLSQ_ADDR_MODE_CNTL            0xBE05



/* VFD registers */

#define A6XX_VFD_ADDR_MODE_CNTL             0xA601



/* VPC registers */

#define A6XX_VPC_ADDR_MODE_CNTL             0x9601



/* UCHE registers */

#define A6XX_UCHE_ADDR_MODE_CNTL            0xE00

#define A6XX_UCHE_MODE_CNTL                 0xE01

#define A6XX_UCHE_WRITE_RANGE_MAX_LO        0xE05

#define A6XX_UCHE_WRITE_RANGE_MAX_HI        0xE06

#define A6XX_UCHE_WRITE_THRU_BASE_LO        0xE07

#define A6XX_UCHE_WRITE_THRU_BASE_HI        0xE08

#define A6XX_UCHE_TRAP_BASE_LO              0xE09

#define A6XX_UCHE_TRAP_BASE_HI              0xE0A

#define A6XX_UCHE_GMEM_RANGE_MIN_LO         0xE0B

#define A6XX_UCHE_GMEM_RANGE_MIN_HI         0xE0C

#define A6XX_UCHE_GMEM_RANGE_MAX_LO         0xE0D

#define A6XX_UCHE_GMEM_RANGE_MAX_HI         0xE0E

#define A6XX_UCHE_CACHE_WAYS                0xE17

#define A6XX_UCHE_FILTER_CNTL               0xE18



/* SP registers */

#define A6XX_SP_ADDR_MODE_CNTL              0xAE01

#define A6XX_SP_NC_MODE_CNTL                0xAE02



/* TP registers */

#define A6XX_TPL1_ADDR_MODE_CNTL            0xB601

#define A6XX_TPL1_NC_MODE_CNTL              0xB604



/* VBIF registers */

#define A6XX_VBIF_VERSION                       0x3000

#define A6XX_VBIF_GATE_OFF_WRREQ_EN             0x302A

#define A6XX_VBIF_XIN_HALT_CTRL0                0x3080

#define A6XX_VBIF_XIN_HALT_CTRL1                0x3081



/* GMU registers */

#define A6XX_GMU_CX_ALWAYS_ON_COUNTER_L         0x1f888

#define A6XX_GMU_CX_ALWAYS_ON_COUNTER_H         0x1f889



#endif /* _A6XX_REG_H */

drivers/gpu/msm/adreno-gpulist.h

+12 −0
Original line number Diff line number Diff line
@@ -304,4 +304,16 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A630,

		.core = 6,

		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT,

		.sqefw_name = "a630_sqe.fw",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

	},

};

drivers/gpu/msm/adreno.c

+18 −11
Original line number Diff line number Diff line
@@ -91,9 +91,13 @@ static struct adreno_device device_3d0 = { 
		.mem_log = KGSL_LOG_LEVEL_DEFAULT,

		.pwr_log = KGSL_LOG_LEVEL_DEFAULT,

	},

	.fw[0] = {

		.fwvirt = NULL

	},

	.fw[1] = {

		.fwvirt = NULL

	},

	.gmem_size = SZ_256K,

	.pfp_fw = NULL,

	.pm4_fw = NULL,

	.ft_policy = KGSL_FT_DEFAULT_POLICY,

	.ft_pf_policy = KGSL_FT_PAGEFAULT_DEFAULT_POLICY,

	.long_ib_detect = 1,
@@ -1035,22 +1039,24 @@ static int adreno_probe(struct platform_device *pdev) 
static void _adreno_free_memories(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);

	struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);



	if (test_bit(ADRENO_DEVICE_DRAWOBJ_PROFILE, &adreno_dev->priv))

		kgsl_free_global(device, &adreno_dev->profile_buffer);



	/* Free local copies of firmware and other command streams */

	kfree(adreno_dev->pfp_fw);

	adreno_dev->pfp_fw = NULL;

	kfree(pfp_fw->fwvirt);

	pfp_fw->fwvirt = NULL;



	kfree(adreno_dev->pm4_fw);

	adreno_dev->pm4_fw = NULL;

	kfree(pm4_fw->fwvirt);

	pm4_fw->fwvirt = NULL;



	kfree(adreno_dev->gpmu_cmds);

	adreno_dev->gpmu_cmds = NULL;



	kgsl_free_global(device, &adreno_dev->pm4);

	kgsl_free_global(device, &adreno_dev->pfp);

	kgsl_free_global(device, &pfp_fw->memdesc);

	kgsl_free_global(device, &pm4_fw->memdesc);

}



static int adreno_remove(struct platform_device *pdev)
@@ -1753,7 +1759,8 @@ static int adreno_getproperty(struct kgsl_device *device, 
		{

			uint64_t gmem_vaddr = 0;



			if (adreno_is_a5xx(adreno_dev))

			if (adreno_is_a5xx(adreno_dev) ||

					adreno_is_a6xx(adreno_dev))

				gmem_vaddr = ADRENO_UCHE_GMEM_BASE;

			if (sizebytes != sizeof(uint64_t)) {

				status = -EINVAL;
@@ -1797,8 +1804,8 @@ static int adreno_getproperty(struct kgsl_device *device, 
			}

			memset(&ucode, 0, sizeof(ucode));



			ucode.pfp = adreno_dev->pfp_fw_version;

			ucode.pm4 = adreno_dev->pm4_fw_version;

			ucode.pfp = adreno_dev->fw[ADRENO_FW_PFP].version;

			ucode.pm4 = adreno_dev->fw[ADRENO_FW_PM4].version;



			if (copy_to_user(value, &ucode, sizeof(ucode))) {

				status = -EFAULT;

drivers/gpu/msm/adreno.h

+36 −12
Original line number Diff line number Diff line
@@ -85,6 +85,8 @@ 
#define ADRENO_DRAWOBJ_RB(c)			\

	((ADRENO_CONTEXT(c->context))->rb)



#define ADRENO_FW(a, f)		(&(a->fw[f]))



/* Adreno core features */

/* The core uses OCMEM for GMEM/binning memory */

#define ADRENO_USES_OCMEM     BIT(0)
@@ -154,6 +156,10 @@ 


#define ADRENO_UCHE_GMEM_BASE	0x100000



#define ADRENO_FW_PFP 0

#define ADRENO_FW_SQE 0

#define ADRENO_FW_PM4 1



enum adreno_gpurev {

	ADRENO_REV_UNKNOWN = 0,

	ADRENO_REV_A304 = 304,
@@ -175,6 +181,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A512 = 512,

	ADRENO_REV_A530 = 530,

	ADRENO_REV_A540 = 540,

	ADRENO_REV_A630 = 630,

};



#define ADRENO_START_WARM 0
@@ -252,6 +259,20 @@ struct adreno_busy_data { 
	unsigned int throttle_cycles[ADRENO_GPMU_THROTTLE_COUNTERS];

};



/**

 * struct adreno_firmware - Struct holding fw details

 * @fwvirt: Buffer which holds the ucode

 * @size: Size of ucode buffer

 * @version: Version of ucode

 * @memdesc: Memory descriptor which holds ucode buffer info

 */

struct adreno_firmware {

	unsigned int *fwvirt;

	size_t size;

	unsigned int version;

	struct kgsl_memdesc memdesc;

};



/**

 * struct adreno_gpu_core - A specific GPU core definition

 * @gpurev: Unique GPU revision identifier
@@ -292,6 +313,7 @@ struct adreno_gpu_core { 
	unsigned long features;

	const char *pm4fw_name;

	const char *pfpfw_name;

	const char *sqefw_name;

	const char *zap_name;

	struct adreno_gpudev *gpudev;

	size_t gmem_size;
@@ -380,14 +402,7 @@ struct adreno_device { 
	unsigned long gmem_base;

	unsigned long gmem_size;

	const struct adreno_gpu_core *gpucore;

	unsigned int *pfp_fw;

	size_t pfp_fw_size;

	unsigned int pfp_fw_version;

	struct kgsl_memdesc pfp;

	unsigned int *pm4_fw;

	size_t pm4_fw_size;

	unsigned int pm4_fw_version;

	struct kgsl_memdesc pm4;

	struct adreno_firmware fw[2];

	size_t gpmu_cmds_size;

	unsigned int *gpmu_cmds;

	struct adreno_ringbuffer ringbuffers[KGSL_PRIORITY_MAX_RB_LEVELS];
@@ -874,6 +889,7 @@ extern unsigned int *adreno_ft_regs_val; 
extern struct adreno_gpudev adreno_a3xx_gpudev;

extern struct adreno_gpudev adreno_a4xx_gpudev;

extern struct adreno_gpudev adreno_a5xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gpudev;



extern int adreno_wake_nice;

extern unsigned int adreno_wake_timeout;
@@ -1045,6 +1061,14 @@ static inline int adreno_is_a540v2(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1);

}



static inline int adreno_is_a6xx(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 600 &&

			ADRENO_GPUREV(adreno_dev) < 700;

}



ADRENO_TARGET(a630, ADRENO_REV_A630)



/*

 * adreno_checkreg_off() - Checks the validity of a register enum

 * @adreno_dev:		Pointer to adreno device
@@ -1331,10 +1355,10 @@ static inline void adreno_context_debugfs_init(struct adreno_device *device, 
static inline int adreno_compare_pm4_version(struct adreno_device *adreno_dev,

	unsigned int version)

{

	if (adreno_dev->pm4_fw_version == version)

	if (adreno_dev->fw[ADRENO_FW_PM4].version == version)

		return 0;



	return (adreno_dev->pm4_fw_version > version) ? 1 : -1;

	return (adreno_dev->fw[ADRENO_FW_PM4].version > version) ? 1 : -1;

}



/**
@@ -1348,10 +1372,10 @@ static inline int adreno_compare_pm4_version(struct adreno_device *adreno_dev, 
static inline int adreno_compare_pfp_version(struct adreno_device *adreno_dev,

	unsigned int version)

{

	if (adreno_dev->pfp_fw_version == version)

	if (adreno_dev->fw[ADRENO_FW_PFP].version == version)

		return 0;



	return (adreno_dev->pfp_fw_version > version) ? 1 : -1;

	return (adreno_dev->fw[ADRENO_FW_PFP].version > version) ? 1 : -1;

}



/*