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Commit 704b93b3 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
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msm: clk: qcom: upstream clock framework support on 10nm MDSS PLL 



Configure MDSS DSI PLL using upstream clock framework APIs on 10 nm
PLL driver

Change-Id: Ic5ce623a6767d4f3a273ebbde8747ec35fe23c03
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 49ae9119
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